QT5201U wiki - User contributions [en]

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-30T09:43:53Z

Chua Rui Ming: /* Summary Table */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
=====Product=====

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

=====Architecture=====

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

=====Preview=====

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. There are two reasons for our choice: Firstly, this simplifies the problem. Secondly, this way, we obtain two pulses for every set of clock signals- At the front-end and tail-end of the first and second clock signals respectively:

<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


[[File:2-Figure3-2.png||350px]]

For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

=====FPGA Top Design=====

[[File:Top_Design.png|1200px]]

The bulk of our efforts went into the code to configure the Nanosecond Pulse Generator. The FPGA Top Design summarises the outcome of our efforts. Our efforts in its entirety could be found here https://drive.google.com/drive/folders/1weGO1Lyi6H_-A1OadQFYIO-wQEv0VXFj?usp=sharing which will lead to a Google Drive where our files are uploaded in its entirety.

FPGA Performance Characterisation

To characterise the performance of our FPGA, we measured the pulses produced by our FPGA with an oscilloscope (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals, and/or the frequency of the clock signals (which can be adjusted in integer multiples of the clock oscillator), we can obtain different performances (in terms of pulse widths and frequencies) of our pulses.
 
 
=====Best Overall Performance=====

The best overall performance was obtained when the phase difference between the clock signals was set at 11.25 degrees while the frequency of the clock signal is 150MHZ. We obtained a pulse width of 637ps at a frequency of 150MHZ.

[[File:d11.25f150_Best_Performance.png|600px]]

Unfortunately, pushing the FPGA further, we were unable to obtain narrower pulses with that higher frequencies.

[[File:D10f200 Too High Frequency For Pulse Width.png||600px]]

=====Highest Frequency=====

The best frequency performance was obtained when the phase difference between the clock signals was set at 15 degrees while the frequency of the clock signal is 200MHZ. We obtained a pulse width of 746 ps at a frequency of 200MHZ.

[[File:D15f200 _Best _Frequency.png||600px]]

=====Results as a Function of Phase Difference=====

We recall from "Methods" that the way to obtain the pulses was to carve the pulses out from two clock signals. Theoretically, the pulse duration should increase with phase difference for the same frequency. When the phase difference between the clock signals were set at 9, 18 and 37.5 degrees and the frequency of the clock signal is 100MHZ, we obtained a pulse width of 805 ps, pulse width of 1.2 ns and pulse width of 2.27ns respectively.

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D18f100_Function_Of_Phase_Difference_2.png||600px]]

[[File:D37.5f100_Function_Of_Phase_Difference_3.png||600px]]

=====Different Configurations For The Same Pulse Width (Theoretically)=====

Theoretically, the pulse duration should remain the same if the phase difference and frequency were increased with the same multiple. The plots below feature such a set of measurements. Setting aside some margin of error for the fact that the increase was not in perfect multiples because of the limited step control of the phase difference, as well as the different frequency response of the circuit, this phenomenon was more or less observed.

[[File:D3.37f50.png||600px]]

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D11.25f150_Best_Performance.png||600px]]

=====Summary Table=====

[[File:Table.png||800px]]

====Application====

While we have achieved our goal of creating a working Nanosecond Pulse Generator with our FPGA, it is important to recognise the fact that the pulses created by the FPGA belong to low-power pulse signals between 1.2-3.3V based on the specific I/O standard for the FPGA. Amplification may be required for our FPGA to work with other devices. In this section, a resistance network with a transistor was designed to amplify the output pulses from our FPGA up to 7V for an Electro Optic Modulator (EOM).

As shown in the picture, a TIP29C NPN transistor in our possession was hired as the amplification component. The grounded resistor R4 represents the inner impedance of the EOM. Unfortunately, the 7V half-wave voltage of the EOM required a relatively high current which caused the transistor to overheat. Such issues have to be taken into consideration and represent our future work. Other users would have to consider their own power amplification needs.

[[File:Amplifier.png||400px]]

[[File:Amplifer_2.jpg||300px]]

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-30T09:43:42Z

Chua Rui Ming: /* Summary Table */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
=====Product=====

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

=====Architecture=====

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

=====Preview=====

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. There are two reasons for our choice: Firstly, this simplifies the problem. Secondly, this way, we obtain two pulses for every set of clock signals- At the front-end and tail-end of the first and second clock signals respectively:

<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


[[File:2-Figure3-2.png||350px]]

For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

=====FPGA Top Design=====

[[File:Top_Design.png|1200px]]

The bulk of our efforts went into the code to configure the Nanosecond Pulse Generator. The FPGA Top Design summarises the outcome of our efforts. Our efforts in its entirety could be found here https://drive.google.com/drive/folders/1weGO1Lyi6H_-A1OadQFYIO-wQEv0VXFj?usp=sharing which will lead to a Google Drive where our files are uploaded in its entirety.

FPGA Performance Characterisation

To characterise the performance of our FPGA, we measured the pulses produced by our FPGA with an oscilloscope (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals, and/or the frequency of the clock signals (which can be adjusted in integer multiples of the clock oscillator), we can obtain different performances (in terms of pulse widths and frequencies) of our pulses.
 
 
=====Best Overall Performance=====

The best overall performance was obtained when the phase difference between the clock signals was set at 11.25 degrees while the frequency of the clock signal is 150MHZ. We obtained a pulse width of 637ps at a frequency of 150MHZ.

[[File:d11.25f150_Best_Performance.png|600px]]

Unfortunately, pushing the FPGA further, we were unable to obtain narrower pulses with that higher frequencies.

[[File:D10f200 Too High Frequency For Pulse Width.png||600px]]

=====Highest Frequency=====

The best frequency performance was obtained when the phase difference between the clock signals was set at 15 degrees while the frequency of the clock signal is 200MHZ. We obtained a pulse width of 746 ps at a frequency of 200MHZ.

[[File:D15f200 _Best _Frequency.png||600px]]

=====Results as a Function of Phase Difference=====

We recall from "Methods" that the way to obtain the pulses was to carve the pulses out from two clock signals. Theoretically, the pulse duration should increase with phase difference for the same frequency. When the phase difference between the clock signals were set at 9, 18 and 37.5 degrees and the frequency of the clock signal is 100MHZ, we obtained a pulse width of 805 ps, pulse width of 1.2 ns and pulse width of 2.27ns respectively.

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D18f100_Function_Of_Phase_Difference_2.png||600px]]

[[File:D37.5f100_Function_Of_Phase_Difference_3.png||600px]]

=====Different Configurations For The Same Pulse Width (Theoretically)=====

Theoretically, the pulse duration should remain the same if the phase difference and frequency were increased with the same multiple. The plots below feature such a set of measurements. Setting aside some margin of error for the fact that the increase was not in perfect multiples because of the limited step control of the phase difference, as well as the different frequency response of the circuit, this phenomenon was more or less observed.

[[File:D3.37f50.png||600px]]

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D11.25f150_Best_Performance.png||600px]]

=====Summary Table=====

[[File:Table.png||700px]]

====Application====

While we have achieved our goal of creating a working Nanosecond Pulse Generator with our FPGA, it is important to recognise the fact that the pulses created by the FPGA belong to low-power pulse signals between 1.2-3.3V based on the specific I/O standard for the FPGA. Amplification may be required for our FPGA to work with other devices. In this section, a resistance network with a transistor was designed to amplify the output pulses from our FPGA up to 7V for an Electro Optic Modulator (EOM).

As shown in the picture, a TIP29C NPN transistor in our possession was hired as the amplification component. The grounded resistor R4 represents the inner impedance of the EOM. Unfortunately, the 7V half-wave voltage of the EOM required a relatively high current which caused the transistor to overheat. Such issues have to be taken into consideration and represent our future work. Other users would have to consider their own power amplification needs.

[[File:Amplifier.png||400px]]

[[File:Amplifer_2.jpg||300px]]

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-30T09:43:23Z

Chua Rui Ming: /* Application */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
=====Product=====

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

=====Architecture=====

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

=====Preview=====

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. There are two reasons for our choice: Firstly, this simplifies the problem. Secondly, this way, we obtain two pulses for every set of clock signals- At the front-end and tail-end of the first and second clock signals respectively:

<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


[[File:2-Figure3-2.png||350px]]

For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

=====FPGA Top Design=====

[[File:Top_Design.png|1200px]]

The bulk of our efforts went into the code to configure the Nanosecond Pulse Generator. The FPGA Top Design summarises the outcome of our efforts. Our efforts in its entirety could be found here https://drive.google.com/drive/folders/1weGO1Lyi6H_-A1OadQFYIO-wQEv0VXFj?usp=sharing which will lead to a Google Drive where our files are uploaded in its entirety.

FPGA Performance Characterisation

To characterise the performance of our FPGA, we measured the pulses produced by our FPGA with an oscilloscope (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals, and/or the frequency of the clock signals (which can be adjusted in integer multiples of the clock oscillator), we can obtain different performances (in terms of pulse widths and frequencies) of our pulses.
 
 
=====Best Overall Performance=====

The best overall performance was obtained when the phase difference between the clock signals was set at 11.25 degrees while the frequency of the clock signal is 150MHZ. We obtained a pulse width of 637ps at a frequency of 150MHZ.

[[File:d11.25f150_Best_Performance.png|600px]]

Unfortunately, pushing the FPGA further, we were unable to obtain narrower pulses with that higher frequencies.

[[File:D10f200 Too High Frequency For Pulse Width.png||600px]]

=====Highest Frequency=====

The best frequency performance was obtained when the phase difference between the clock signals was set at 15 degrees while the frequency of the clock signal is 200MHZ. We obtained a pulse width of 746 ps at a frequency of 200MHZ.

[[File:D15f200 _Best _Frequency.png||600px]]

=====Results as a Function of Phase Difference=====

We recall from "Methods" that the way to obtain the pulses was to carve the pulses out from two clock signals. Theoretically, the pulse duration should increase with phase difference for the same frequency. When the phase difference between the clock signals were set at 9, 18 and 37.5 degrees and the frequency of the clock signal is 100MHZ, we obtained a pulse width of 805 ps, pulse width of 1.2 ns and pulse width of 2.27ns respectively.

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D18f100_Function_Of_Phase_Difference_2.png||600px]]

[[File:D37.5f100_Function_Of_Phase_Difference_3.png||600px]]

=====Different Configurations For The Same Pulse Width (Theoretically)=====

Theoretically, the pulse duration should remain the same if the phase difference and frequency were increased with the same multiple. The plots below feature such a set of measurements. Setting aside some margin of error for the fact that the increase was not in perfect multiples because of the limited step control of the phase difference, as well as the different frequency response of the circuit, this phenomenon was more or less observed.

[[File:D3.37f50.png||600px]]

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D11.25f150_Best_Performance.png||600px]]

=====Summary Table=====

[[File:Table.png||600px]]

====Application====

While we have achieved our goal of creating a working Nanosecond Pulse Generator with our FPGA, it is important to recognise the fact that the pulses created by the FPGA belong to low-power pulse signals between 1.2-3.3V based on the specific I/O standard for the FPGA. Amplification may be required for our FPGA to work with other devices. In this section, a resistance network with a transistor was designed to amplify the output pulses from our FPGA up to 7V for an Electro Optic Modulator (EOM).

As shown in the picture, a TIP29C NPN transistor in our possession was hired as the amplification component. The grounded resistor R4 represents the inner impedance of the EOM. Unfortunately, the 7V half-wave voltage of the EOM required a relatively high current which caused the transistor to overheat. Such issues have to be taken into consideration and represent our future work. Other users would have to consider their own power amplification needs.

[[File:Amplifier.png||400px]]

[[File:Amplifer_2.jpg||300px]]

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-30T09:42:43Z

Chua Rui Ming: /* Application */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
=====Product=====

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

=====Architecture=====

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

=====Preview=====

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. There are two reasons for our choice: Firstly, this simplifies the problem. Secondly, this way, we obtain two pulses for every set of clock signals- At the front-end and tail-end of the first and second clock signals respectively:

<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


[[File:2-Figure3-2.png||350px]]

For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

=====FPGA Top Design=====

[[File:Top_Design.png|1200px]]

The bulk of our efforts went into the code to configure the Nanosecond Pulse Generator. The FPGA Top Design summarises the outcome of our efforts. Our efforts in its entirety could be found here https://drive.google.com/drive/folders/1weGO1Lyi6H_-A1OadQFYIO-wQEv0VXFj?usp=sharing which will lead to a Google Drive where our files are uploaded in its entirety.

FPGA Performance Characterisation

To characterise the performance of our FPGA, we measured the pulses produced by our FPGA with an oscilloscope (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals, and/or the frequency of the clock signals (which can be adjusted in integer multiples of the clock oscillator), we can obtain different performances (in terms of pulse widths and frequencies) of our pulses.
 
 
=====Best Overall Performance=====

The best overall performance was obtained when the phase difference between the clock signals was set at 11.25 degrees while the frequency of the clock signal is 150MHZ. We obtained a pulse width of 637ps at a frequency of 150MHZ.

[[File:d11.25f150_Best_Performance.png|600px]]

Unfortunately, pushing the FPGA further, we were unable to obtain narrower pulses with that higher frequencies.

[[File:D10f200 Too High Frequency For Pulse Width.png||600px]]

=====Highest Frequency=====

The best frequency performance was obtained when the phase difference between the clock signals was set at 15 degrees while the frequency of the clock signal is 200MHZ. We obtained a pulse width of 746 ps at a frequency of 200MHZ.

[[File:D15f200 _Best _Frequency.png||600px]]

=====Results as a Function of Phase Difference=====

We recall from "Methods" that the way to obtain the pulses was to carve the pulses out from two clock signals. Theoretically, the pulse duration should increase with phase difference for the same frequency. When the phase difference between the clock signals were set at 9, 18 and 37.5 degrees and the frequency of the clock signal is 100MHZ, we obtained a pulse width of 805 ps, pulse width of 1.2 ns and pulse width of 2.27ns respectively.

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D18f100_Function_Of_Phase_Difference_2.png||600px]]

[[File:D37.5f100_Function_Of_Phase_Difference_3.png||600px]]

=====Different Configurations For The Same Pulse Width (Theoretically)=====

Theoretically, the pulse duration should remain the same if the phase difference and frequency were increased with the same multiple. The plots below feature such a set of measurements. Setting aside some margin of error for the fact that the increase was not in perfect multiples because of the limited step control of the phase difference, as well as the different frequency response of the circuit, this phenomenon was more or less observed.

[[File:D3.37f50.png||600px]]

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D11.25f150_Best_Performance.png||600px]]

=====Summary Table=====

[[File:Table.png||600px]]

====Application====

While we have achieved our goal of creating a working Nanosecond Pulse Generator with our FPGA, it is important to recognise the fact that the pulses created by the FPGA belong to low-power pulse signals between 1.2-3.3V based on the specific I/O standard for the FPGA. Amplification may be required for our FPGA to work with other devices. In this section, a resistance network with a transistor was designed to amplify the output pulses from our FPGA up to 7V for an Electro Optic Modulator (EOM).

As shown in the picture, a TIP29C NPN transistor in our possession was hired as the amplification component. The grounded resistor R4 represents the inner impedance of the EOM. Unfortunately, the 7V half-wave voltage of the EOM required a relatively high current which caused the transistor to overheat. Such issues have to be taken into consideration and represent our future work. Other users would have to consider their own power amplication needs.

[[File:Amplifier.png||400px]]

[[File:Amplifer_2.jpg||300px]]

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-30T09:42:23Z

Chua Rui Ming: /* Application */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
=====Product=====

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

=====Architecture=====

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

=====Preview=====

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. There are two reasons for our choice: Firstly, this simplifies the problem. Secondly, this way, we obtain two pulses for every set of clock signals- At the front-end and tail-end of the first and second clock signals respectively:

<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


[[File:2-Figure3-2.png||350px]]

For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

=====FPGA Top Design=====

[[File:Top_Design.png|1200px]]

The bulk of our efforts went into the code to configure the Nanosecond Pulse Generator. The FPGA Top Design summarises the outcome of our efforts. Our efforts in its entirety could be found here https://drive.google.com/drive/folders/1weGO1Lyi6H_-A1OadQFYIO-wQEv0VXFj?usp=sharing which will lead to a Google Drive where our files are uploaded in its entirety.

FPGA Performance Characterisation

To characterise the performance of our FPGA, we measured the pulses produced by our FPGA with an oscilloscope (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals, and/or the frequency of the clock signals (which can be adjusted in integer multiples of the clock oscillator), we can obtain different performances (in terms of pulse widths and frequencies) of our pulses.
 
 
=====Best Overall Performance=====

The best overall performance was obtained when the phase difference between the clock signals was set at 11.25 degrees while the frequency of the clock signal is 150MHZ. We obtained a pulse width of 637ps at a frequency of 150MHZ.

[[File:d11.25f150_Best_Performance.png|600px]]

Unfortunately, pushing the FPGA further, we were unable to obtain narrower pulses with that higher frequencies.

[[File:D10f200 Too High Frequency For Pulse Width.png||600px]]

=====Highest Frequency=====

The best frequency performance was obtained when the phase difference between the clock signals was set at 15 degrees while the frequency of the clock signal is 200MHZ. We obtained a pulse width of 746 ps at a frequency of 200MHZ.

[[File:D15f200 _Best _Frequency.png||600px]]

=====Results as a Function of Phase Difference=====

We recall from "Methods" that the way to obtain the pulses was to carve the pulses out from two clock signals. Theoretically, the pulse duration should increase with phase difference for the same frequency. When the phase difference between the clock signals were set at 9, 18 and 37.5 degrees and the frequency of the clock signal is 100MHZ, we obtained a pulse width of 805 ps, pulse width of 1.2 ns and pulse width of 2.27ns respectively.

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D18f100_Function_Of_Phase_Difference_2.png||600px]]

[[File:D37.5f100_Function_Of_Phase_Difference_3.png||600px]]

=====Different Configurations For The Same Pulse Width (Theoretically)=====

Theoretically, the pulse duration should remain the same if the phase difference and frequency were increased with the same multiple. The plots below feature such a set of measurements. Setting aside some margin of error for the fact that the increase was not in perfect multiples because of the limited step control of the phase difference, as well as the different frequency response of the circuit, this phenomenon was more or less observed.

[[File:D3.37f50.png||600px]]

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D11.25f150_Best_Performance.png||600px]]

=====Summary Table=====

[[File:Table.png||600px]]

====Application====

While we have achieved our goal of creating a working Nanosecond Pulse Generator with our FPGA, it is important to recognise the fact that the pulses created by the FPGA belong to low-power pulse signals between 1.2-3.3V based on the specific I/O standard for the FPGA. Amplification may be required for our FPGA to work with other devices. In this section, a resistance network with a transistor was designed to amplify the output pulses from our FPGA up to 7V for an Electro Optic Modulator (EOM).

As shown in the picture, a TIP29C NPN transistor in our possession was hired as the amplification component. The grounded resistor R4 represents the inner impedance of the EOM. Unfortunately, the 7V half-wave voltage of the EOM required a relatively high current which caused the transistor to overheat. Such issues have to be taken into consideration and represent our future work. We then leave other users to consider their own power amplication needs.

[[File:Amplifier.png||400px]]

[[File:Amplifer_2.jpg||300px]]

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-30T09:41:51Z

Chua Rui Ming: /* Application */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
=====Product=====

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

=====Architecture=====

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

=====Preview=====

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. There are two reasons for our choice: Firstly, this simplifies the problem. Secondly, this way, we obtain two pulses for every set of clock signals- At the front-end and tail-end of the first and second clock signals respectively:

<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


[[File:2-Figure3-2.png||350px]]

For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

=====FPGA Top Design=====

[[File:Top_Design.png|1200px]]

The bulk of our efforts went into the code to configure the Nanosecond Pulse Generator. The FPGA Top Design summarises the outcome of our efforts. Our efforts in its entirety could be found here https://drive.google.com/drive/folders/1weGO1Lyi6H_-A1OadQFYIO-wQEv0VXFj?usp=sharing which will lead to a Google Drive where our files are uploaded in its entirety.

FPGA Performance Characterisation

To characterise the performance of our FPGA, we measured the pulses produced by our FPGA with an oscilloscope (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals, and/or the frequency of the clock signals (which can be adjusted in integer multiples of the clock oscillator), we can obtain different performances (in terms of pulse widths and frequencies) of our pulses.
 
 
=====Best Overall Performance=====

The best overall performance was obtained when the phase difference between the clock signals was set at 11.25 degrees while the frequency of the clock signal is 150MHZ. We obtained a pulse width of 637ps at a frequency of 150MHZ.

[[File:d11.25f150_Best_Performance.png|600px]]

Unfortunately, pushing the FPGA further, we were unable to obtain narrower pulses with that higher frequencies.

[[File:D10f200 Too High Frequency For Pulse Width.png||600px]]

=====Highest Frequency=====

The best frequency performance was obtained when the phase difference between the clock signals was set at 15 degrees while the frequency of the clock signal is 200MHZ. We obtained a pulse width of 746 ps at a frequency of 200MHZ.

[[File:D15f200 _Best _Frequency.png||600px]]

=====Results as a Function of Phase Difference=====

We recall from "Methods" that the way to obtain the pulses was to carve the pulses out from two clock signals. Theoretically, the pulse duration should increase with phase difference for the same frequency. When the phase difference between the clock signals were set at 9, 18 and 37.5 degrees and the frequency of the clock signal is 100MHZ, we obtained a pulse width of 805 ps, pulse width of 1.2 ns and pulse width of 2.27ns respectively.

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D18f100_Function_Of_Phase_Difference_2.png||600px]]

[[File:D37.5f100_Function_Of_Phase_Difference_3.png||600px]]

=====Different Configurations For The Same Pulse Width (Theoretically)=====

Theoretically, the pulse duration should remain the same if the phase difference and frequency were increased with the same multiple. The plots below feature such a set of measurements. Setting aside some margin of error for the fact that the increase was not in perfect multiples because of the limited step control of the phase difference, as well as the different frequency response of the circuit, this phenomenon was more or less observed.

[[File:D3.37f50.png||600px]]

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D11.25f150_Best_Performance.png||600px]]

=====Summary Table=====

[[File:Table.png||600px]]

====Application====

While we have achieved our goal of creating a working Nanosecond Pulse Generator with our FPGA, it is important to recognise the fact that the pulses created by the FPGA belong to low-power pulse signals between 1.2-3.3V based on the specific I/O standard for the FPGA. Amplification may be required for our FPGA to work with other devices. In this section, a resistance network with a transistor was designed to amplify the output pulses from our FPGA up to 7V for an Electro Optic Modulator (EOM).

As shown in the picture, a TIP29C NPN transistor in our possession was hired as the amplification component. The grounded resistor R4 represents the inner impedance of the EOM. Unfortunately, the 7V half-wave voltage of the EOM required a relatively high current which caused the transistor to overheat. Such issues have to be taken into consideration and represent our future work. We leave other users to consider their own power amplication needs.

[[File:Amplifier.png||400px]]

[[File:Amplifer_2.jpg||300px]]

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-30T09:38:32Z

Chua Rui Ming: /* Application */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
=====Product=====

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

=====Architecture=====

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

=====Preview=====

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. There are two reasons for our choice: Firstly, this simplifies the problem. Secondly, this way, we obtain two pulses for every set of clock signals- At the front-end and tail-end of the first and second clock signals respectively:

<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


[[File:2-Figure3-2.png||350px]]

For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

=====FPGA Top Design=====

[[File:Top_Design.png|1200px]]

The bulk of our efforts went into the code to configure the Nanosecond Pulse Generator. The FPGA Top Design summarises the outcome of our efforts. Our efforts in its entirety could be found here https://drive.google.com/drive/folders/1weGO1Lyi6H_-A1OadQFYIO-wQEv0VXFj?usp=sharing which will lead to a Google Drive where our files are uploaded in its entirety.

FPGA Performance Characterisation

To characterise the performance of our FPGA, we measured the pulses produced by our FPGA with an oscilloscope (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals, and/or the frequency of the clock signals (which can be adjusted in integer multiples of the clock oscillator), we can obtain different performances (in terms of pulse widths and frequencies) of our pulses.
 
 
=====Best Overall Performance=====

The best overall performance was obtained when the phase difference between the clock signals was set at 11.25 degrees while the frequency of the clock signal is 150MHZ. We obtained a pulse width of 637ps at a frequency of 150MHZ.

[[File:d11.25f150_Best_Performance.png|600px]]

Unfortunately, pushing the FPGA further, we were unable to obtain narrower pulses with that higher frequencies.

[[File:D10f200 Too High Frequency For Pulse Width.png||600px]]

=====Highest Frequency=====

The best frequency performance was obtained when the phase difference between the clock signals was set at 15 degrees while the frequency of the clock signal is 200MHZ. We obtained a pulse width of 746 ps at a frequency of 200MHZ.

[[File:D15f200 _Best _Frequency.png||600px]]

=====Results as a Function of Phase Difference=====

We recall from "Methods" that the way to obtain the pulses was to carve the pulses out from two clock signals. Theoretically, the pulse duration should increase with phase difference for the same frequency. When the phase difference between the clock signals were set at 9, 18 and 37.5 degrees and the frequency of the clock signal is 100MHZ, we obtained a pulse width of 805 ps, pulse width of 1.2 ns and pulse width of 2.27ns respectively.

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D18f100_Function_Of_Phase_Difference_2.png||600px]]

[[File:D37.5f100_Function_Of_Phase_Difference_3.png||600px]]

=====Different Configurations For The Same Pulse Width (Theoretically)=====

Theoretically, the pulse duration should remain the same if the phase difference and frequency were increased with the same multiple. The plots below feature such a set of measurements. Setting aside some margin of error for the fact that the increase was not in perfect multiples because of the limited step control of the phase difference, as well as the different frequency response of the circuit, this phenomenon was more or less observed.

[[File:D3.37f50.png||600px]]

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D11.25f150_Best_Performance.png||600px]]

=====Summary Table=====

[[File:Table.png||600px]]

====Application====

While we have achieved our goal of creating a working Nanosecond Pulse Generator with our FPGA, it is important to recognise the fact that the pulses created by the FPGA belong to low-power pulse signals between 1.2-3.3V based on the specific I/O standard for the FPGA. Amplification may be required for our FPGA to work with other devices. In this section, a resistance network with a transistor was designed to amplify the output pulses from our FPGA up to 7V for an Electro Optic Modulator (EOM).

As shown in the picture, a TIP29C NPN transistor in our possession was hired as the amplification component. The grounded resistor R4 represents the inner impedance of the EOM. Unfortunately, the 7V half-wave voltage of the EOM required a relatively high current which caused the transistor to overheat. We leave future users to consider their own power amplication needs.

[[File:Amplifier.png||400px]]

[[File:Amplifer_2.jpg||300px]]

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-30T09:35:30Z

Chua Rui Ming: /* Application */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
=====Product=====

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

=====Architecture=====

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

=====Preview=====

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. There are two reasons for our choice: Firstly, this simplifies the problem. Secondly, this way, we obtain two pulses for every set of clock signals- At the front-end and tail-end of the first and second clock signals respectively:

<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


[[File:2-Figure3-2.png||350px]]

For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

=====FPGA Top Design=====

[[File:Top_Design.png|1200px]]

The bulk of our efforts went into the code to configure the Nanosecond Pulse Generator. The FPGA Top Design summarises the outcome of our efforts. Our efforts in its entirety could be found here https://drive.google.com/drive/folders/1weGO1Lyi6H_-A1OadQFYIO-wQEv0VXFj?usp=sharing which will lead to a Google Drive where our files are uploaded in its entirety.

FPGA Performance Characterisation

To characterise the performance of our FPGA, we measured the pulses produced by our FPGA with an oscilloscope (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals, and/or the frequency of the clock signals (which can be adjusted in integer multiples of the clock oscillator), we can obtain different performances (in terms of pulse widths and frequencies) of our pulses.
 
 
=====Best Overall Performance=====

The best overall performance was obtained when the phase difference between the clock signals was set at 11.25 degrees while the frequency of the clock signal is 150MHZ. We obtained a pulse width of 637ps at a frequency of 150MHZ.

[[File:d11.25f150_Best_Performance.png|600px]]

Unfortunately, pushing the FPGA further, we were unable to obtain narrower pulses with that higher frequencies.

[[File:D10f200 Too High Frequency For Pulse Width.png||600px]]

=====Highest Frequency=====

The best frequency performance was obtained when the phase difference between the clock signals was set at 15 degrees while the frequency of the clock signal is 200MHZ. We obtained a pulse width of 746 ps at a frequency of 200MHZ.

[[File:D15f200 _Best _Frequency.png||600px]]

=====Results as a Function of Phase Difference=====

We recall from "Methods" that the way to obtain the pulses was to carve the pulses out from two clock signals. Theoretically, the pulse duration should increase with phase difference for the same frequency. When the phase difference between the clock signals were set at 9, 18 and 37.5 degrees and the frequency of the clock signal is 100MHZ, we obtained a pulse width of 805 ps, pulse width of 1.2 ns and pulse width of 2.27ns respectively.

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D18f100_Function_Of_Phase_Difference_2.png||600px]]

[[File:D37.5f100_Function_Of_Phase_Difference_3.png||600px]]

=====Different Configurations For The Same Pulse Width (Theoretically)=====

Theoretically, the pulse duration should remain the same if the phase difference and frequency were increased with the same multiple. The plots below feature such a set of measurements. Setting aside some margin of error for the fact that the increase was not in perfect multiples because of the limited step control of the phase difference, as well as the different frequency response of the circuit, this phenomenon was more or less observed.

[[File:D3.37f50.png||600px]]

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D11.25f150_Best_Performance.png||600px]]

=====Summary Table=====

[[File:Table.png||600px]]

====Application====

While we have achieved our goal of creating a working Nanosecond Pulse Generator with our FPGA, it is important to recognise the fact that the pulses created by the FPGA belong to low-power pulse signals between 1.2-3.3V based on the specific I/O standard for the FPGA. Amplification may be required for our FPGA to work with other devices. In this section, a resistance network with a transistor was designed to amplify the output pulses from our FPGA up to 7V for an Electro Optic Modulator (EOM).

As shown in the picture, a TIP29C NPN transistor in our possession was hired as the amplification component. The grounded resistor R4 represents the inner impedance of the EOM. Unfortunately, the 7V half-wave voltage of the EOM required a relatively high current which caused the transistor to overheat.

[[File:Amplifier.png||400px]]

[[File:Amplifer_2.jpg||300px]]

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-30T09:34:23Z

Chua Rui Ming: /* Application */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
=====Product=====

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

=====Architecture=====

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

=====Preview=====

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. There are two reasons for our choice: Firstly, this simplifies the problem. Secondly, this way, we obtain two pulses for every set of clock signals- At the front-end and tail-end of the first and second clock signals respectively:

<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


[[File:2-Figure3-2.png||350px]]

For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

=====FPGA Top Design=====

[[File:Top_Design.png|1200px]]

The bulk of our efforts went into the code to configure the Nanosecond Pulse Generator. The FPGA Top Design summarises the outcome of our efforts. Our efforts in its entirety could be found here https://drive.google.com/drive/folders/1weGO1Lyi6H_-A1OadQFYIO-wQEv0VXFj?usp=sharing which will lead to a Google Drive where our files are uploaded in its entirety.

FPGA Performance Characterisation

To characterise the performance of our FPGA, we measured the pulses produced by our FPGA with an oscilloscope (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals, and/or the frequency of the clock signals (which can be adjusted in integer multiples of the clock oscillator), we can obtain different performances (in terms of pulse widths and frequencies) of our pulses.
 
 
=====Best Overall Performance=====

The best overall performance was obtained when the phase difference between the clock signals was set at 11.25 degrees while the frequency of the clock signal is 150MHZ. We obtained a pulse width of 637ps at a frequency of 150MHZ.

[[File:d11.25f150_Best_Performance.png|600px]]

Unfortunately, pushing the FPGA further, we were unable to obtain narrower pulses with that higher frequencies.

[[File:D10f200 Too High Frequency For Pulse Width.png||600px]]

=====Highest Frequency=====

The best frequency performance was obtained when the phase difference between the clock signals was set at 15 degrees while the frequency of the clock signal is 200MHZ. We obtained a pulse width of 746 ps at a frequency of 200MHZ.

[[File:D15f200 _Best _Frequency.png||600px]]

=====Results as a Function of Phase Difference=====

We recall from "Methods" that the way to obtain the pulses was to carve the pulses out from two clock signals. Theoretically, the pulse duration should increase with phase difference for the same frequency. When the phase difference between the clock signals were set at 9, 18 and 37.5 degrees and the frequency of the clock signal is 100MHZ, we obtained a pulse width of 805 ps, pulse width of 1.2 ns and pulse width of 2.27ns respectively.

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D18f100_Function_Of_Phase_Difference_2.png||600px]]

[[File:D37.5f100_Function_Of_Phase_Difference_3.png||600px]]

=====Different Configurations For The Same Pulse Width (Theoretically)=====

Theoretically, the pulse duration should remain the same if the phase difference and frequency were increased with the same multiple. The plots below feature such a set of measurements. Setting aside some margin of error for the fact that the increase was not in perfect multiples because of the limited step control of the phase difference, as well as the different frequency response of the circuit, this phenomenon was more or less observed.

[[File:D3.37f50.png||600px]]

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D11.25f150_Best_Performance.png||600px]]

=====Summary Table=====

[[File:Table.png||600px]]

====Application====

While we have achieved our goal of creating a working Nanosecond Pulse Generator with our FPGA, it is important to recognise the fact that the pulses created by the FPGA belong to low-power pulse signals between 1.2-3.3V based on the specific I/O standard for the FPGA. Amplification may be required for our FPGA to work with other devices. In this section, a resistance network with a transistor was designed to amplify the output pulses from our FPGA up to 7V for an Electro Optic Modulator (EOM).

As shown in the picture, a TIP29C NPN transistor in our possession was hired as the amplification component. The grounded resistor R4 represents the inner impedance of the EOM. Unfortunately, the 7V half-wave voltage of the EOM required a relatively high current which resulted in overheating of the transistor.

[[File:Amplifier.png||400px]]

[[File:Amplifer_2.jpg||300px]]

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-30T09:33:53Z

Chua Rui Ming: /* Application */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
=====Product=====

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

=====Architecture=====

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

=====Preview=====

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. There are two reasons for our choice: Firstly, this simplifies the problem. Secondly, this way, we obtain two pulses for every set of clock signals- At the front-end and tail-end of the first and second clock signals respectively:

<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


[[File:2-Figure3-2.png||350px]]

For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

=====FPGA Top Design=====

[[File:Top_Design.png|1200px]]

The bulk of our efforts went into the code to configure the Nanosecond Pulse Generator. The FPGA Top Design summarises the outcome of our efforts. Our efforts in its entirety could be found here https://drive.google.com/drive/folders/1weGO1Lyi6H_-A1OadQFYIO-wQEv0VXFj?usp=sharing which will lead to a Google Drive where our files are uploaded in its entirety.

FPGA Performance Characterisation

To characterise the performance of our FPGA, we measured the pulses produced by our FPGA with an oscilloscope (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals, and/or the frequency of the clock signals (which can be adjusted in integer multiples of the clock oscillator), we can obtain different performances (in terms of pulse widths and frequencies) of our pulses.
 
 
=====Best Overall Performance=====

The best overall performance was obtained when the phase difference between the clock signals was set at 11.25 degrees while the frequency of the clock signal is 150MHZ. We obtained a pulse width of 637ps at a frequency of 150MHZ.

[[File:d11.25f150_Best_Performance.png|600px]]

Unfortunately, pushing the FPGA further, we were unable to obtain narrower pulses with that higher frequencies.

[[File:D10f200 Too High Frequency For Pulse Width.png||600px]]

=====Highest Frequency=====

The best frequency performance was obtained when the phase difference between the clock signals was set at 15 degrees while the frequency of the clock signal is 200MHZ. We obtained a pulse width of 746 ps at a frequency of 200MHZ.

[[File:D15f200 _Best _Frequency.png||600px]]

=====Results as a Function of Phase Difference=====

We recall from "Methods" that the way to obtain the pulses was to carve the pulses out from two clock signals. Theoretically, the pulse duration should increase with phase difference for the same frequency. When the phase difference between the clock signals were set at 9, 18 and 37.5 degrees and the frequency of the clock signal is 100MHZ, we obtained a pulse width of 805 ps, pulse width of 1.2 ns and pulse width of 2.27ns respectively.

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D18f100_Function_Of_Phase_Difference_2.png||600px]]

[[File:D37.5f100_Function_Of_Phase_Difference_3.png||600px]]

=====Different Configurations For The Same Pulse Width (Theoretically)=====

Theoretically, the pulse duration should remain the same if the phase difference and frequency were increased with the same multiple. The plots below feature such a set of measurements. Setting aside some margin of error for the fact that the increase was not in perfect multiples because of the limited step control of the phase difference, as well as the different frequency response of the circuit, this phenomenon was more or less observed.

[[File:D3.37f50.png||600px]]

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D11.25f150_Best_Performance.png||600px]]

=====Summary Table=====

[[File:Table.png||600px]]

====Application====

While we have achieved our goal of creating a working Nanosecond Pulse Generator with our FPGA, it is important to recognise the fact that the pulses created by the FPGA belong to low-power pulse signals between 1.2-3.3V based on the specific I/O standard for the FPGA. Amplification may be required for our FPGA to work with other devices. In this section, a resistance network with a transistor was designed to amplify the output pulses from our FPGA up to 7V for an Electro Optic Modulator (EOM).

As shown in the picture, a TIP29C NPN transistor in our possession was hired as the amplification component. The grounded resistor R4 represents the inner impedance of the EOM. Unfortunately, the 7V half-wave voltage of the EOM requires a relatively high current which resulted in overheating of the transistor.

[[File:Amplifier.png||400px]]

[[File:Amplifer_2.jpg||300px]]

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-30T09:33:14Z

Chua Rui Ming: /* Application */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
=====Product=====

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

=====Architecture=====

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

=====Preview=====

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. There are two reasons for our choice: Firstly, this simplifies the problem. Secondly, this way, we obtain two pulses for every set of clock signals- At the front-end and tail-end of the first and second clock signals respectively:

<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


[[File:2-Figure3-2.png||350px]]

For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

=====FPGA Top Design=====

[[File:Top_Design.png|1200px]]

The bulk of our efforts went into the code to configure the Nanosecond Pulse Generator. The FPGA Top Design summarises the outcome of our efforts. Our efforts in its entirety could be found here https://drive.google.com/drive/folders/1weGO1Lyi6H_-A1OadQFYIO-wQEv0VXFj?usp=sharing which will lead to a Google Drive where our files are uploaded in its entirety.

FPGA Performance Characterisation

To characterise the performance of our FPGA, we measured the pulses produced by our FPGA with an oscilloscope (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals, and/or the frequency of the clock signals (which can be adjusted in integer multiples of the clock oscillator), we can obtain different performances (in terms of pulse widths and frequencies) of our pulses.
 
 
=====Best Overall Performance=====

The best overall performance was obtained when the phase difference between the clock signals was set at 11.25 degrees while the frequency of the clock signal is 150MHZ. We obtained a pulse width of 637ps at a frequency of 150MHZ.

[[File:d11.25f150_Best_Performance.png|600px]]

Unfortunately, pushing the FPGA further, we were unable to obtain narrower pulses with that higher frequencies.

[[File:D10f200 Too High Frequency For Pulse Width.png||600px]]

=====Highest Frequency=====

The best frequency performance was obtained when the phase difference between the clock signals was set at 15 degrees while the frequency of the clock signal is 200MHZ. We obtained a pulse width of 746 ps at a frequency of 200MHZ.

[[File:D15f200 _Best _Frequency.png||600px]]

=====Results as a Function of Phase Difference=====

We recall from "Methods" that the way to obtain the pulses was to carve the pulses out from two clock signals. Theoretically, the pulse duration should increase with phase difference for the same frequency. When the phase difference between the clock signals were set at 9, 18 and 37.5 degrees and the frequency of the clock signal is 100MHZ, we obtained a pulse width of 805 ps, pulse width of 1.2 ns and pulse width of 2.27ns respectively.

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D18f100_Function_Of_Phase_Difference_2.png||600px]]

[[File:D37.5f100_Function_Of_Phase_Difference_3.png||600px]]

=====Different Configurations For The Same Pulse Width (Theoretically)=====

Theoretically, the pulse duration should remain the same if the phase difference and frequency were increased with the same multiple. The plots below feature such a set of measurements. Setting aside some margin of error for the fact that the increase was not in perfect multiples because of the limited step control of the phase difference, as well as the different frequency response of the circuit, this phenomenon was more or less observed.

[[File:D3.37f50.png||600px]]

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D11.25f150_Best_Performance.png||600px]]

=====Summary Table=====

[[File:Table.png||600px]]

====Application====

While we have achieved our goal of creating a working Nanosecond Pulse Generator with our FPGA, it is important to recognise the fact that the pulses created by the FPGA belong to low-power pulse signals between 1.2-3.3V based on the specific I/O standard for the FPGA. Amplification may be required for our FPGA to work with other devices. In this section, a resistance network with a transistor was designed to amplify the output pulses from our FPGA up to 7V for an Electro Optic Modulator (EOM).

As shown in the picture, a TIP29C NPN transistor was hired as the amplification component. The grounded resistor R4 represents the inner impedance of the EOM. Unfortunately, the 7V half-wave voltage of the EOM requires a relatively high current which resulted in overheating of the transistor.

[[File:Amplifier.png||400px]]

[[File:Amplifer_2.jpg||300px]]

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-30T09:24:45Z

Chua Rui Ming: /* Different Configurations For The Same Pulse Width (Theoretically) */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
=====Product=====

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

=====Architecture=====

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

=====Preview=====

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. There are two reasons for our choice: Firstly, this simplifies the problem. Secondly, this way, we obtain two pulses for every set of clock signals- At the front-end and tail-end of the first and second clock signals respectively:

<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


[[File:2-Figure3-2.png||350px]]

For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

=====FPGA Top Design=====

[[File:Top_Design.png|1200px]]

The bulk of our efforts went into the code to configure the Nanosecond Pulse Generator. The FPGA Top Design summarises the outcome of our efforts. Our efforts in its entirety could be found here https://drive.google.com/drive/folders/1weGO1Lyi6H_-A1OadQFYIO-wQEv0VXFj?usp=sharing which will lead to a Google Drive where our files are uploaded in its entirety.

FPGA Performance Characterisation

To characterise the performance of our FPGA, we measured the pulses produced by our FPGA with an oscilloscope (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals, and/or the frequency of the clock signals (which can be adjusted in integer multiples of the clock oscillator), we can obtain different performances (in terms of pulse widths and frequencies) of our pulses.
 
 
=====Best Overall Performance=====

The best overall performance was obtained when the phase difference between the clock signals was set at 11.25 degrees while the frequency of the clock signal is 150MHZ. We obtained a pulse width of 637ps at a frequency of 150MHZ.

[[File:d11.25f150_Best_Performance.png|600px]]

Unfortunately, pushing the FPGA further, we were unable to obtain narrower pulses with that higher frequencies.

[[File:D10f200 Too High Frequency For Pulse Width.png||600px]]

=====Highest Frequency=====

The best frequency performance was obtained when the phase difference between the clock signals was set at 15 degrees while the frequency of the clock signal is 200MHZ. We obtained a pulse width of 746 ps at a frequency of 200MHZ.

[[File:D15f200 _Best _Frequency.png||600px]]

=====Results as a Function of Phase Difference=====

We recall from "Methods" that the way to obtain the pulses was to carve the pulses out from two clock signals. Theoretically, the pulse duration should increase with phase difference for the same frequency. When the phase difference between the clock signals were set at 9, 18 and 37.5 degrees and the frequency of the clock signal is 100MHZ, we obtained a pulse width of 805 ps, pulse width of 1.2 ns and pulse width of 2.27ns respectively.

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D18f100_Function_Of_Phase_Difference_2.png||600px]]

[[File:D37.5f100_Function_Of_Phase_Difference_3.png||600px]]

=====Different Configurations For The Same Pulse Width (Theoretically)=====

Theoretically, the pulse duration should remain the same if the phase difference and frequency were increased with the same multiple. The plots below feature such a set of measurements. Setting aside some margin of error for the fact that the increase was not in perfect multiples because of the limited step control of the phase difference, as well as the different frequency response of the circuit, this phenomenon was more or less observed.

[[File:D3.37f50.png||600px]]

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D11.25f150_Best_Performance.png||600px]]

=====Summary Table=====

[[File:Table.png||600px]]

====Application====

While we have achieved our goal of creating a working Nanosecond Pulse Generator with our FPGA similar to the works of Zhu & Wang, it is important to recognise the fact that the pulses created by the FPGA belong to low-power pulse signals between 1.2-3.3V based on the specific I/O standard for the FPGA.

Amplification may be required for our FPGA to work with other devices. In this section, we designed an amplifier with the intention of amplifying our pulses up to 7.8V based on the following schematics.

[[File:Amplifier.png||400px]]

[[File:Amplifer_2.jpg||300px]]

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-30T09:20:35Z

Chua Rui Ming: /* Different Configurations For The Same Pulse Width (Theoretically) */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
=====Product=====

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

=====Architecture=====

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

=====Preview=====

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. There are two reasons for our choice: Firstly, this simplifies the problem. Secondly, this way, we obtain two pulses for every set of clock signals- At the front-end and tail-end of the first and second clock signals respectively:

<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


[[File:2-Figure3-2.png||350px]]

For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

=====FPGA Top Design=====

[[File:Top_Design.png|1200px]]

The bulk of our efforts went into the code to configure the Nanosecond Pulse Generator. The FPGA Top Design summarises the outcome of our efforts. Our efforts in its entirety could be found here https://drive.google.com/drive/folders/1weGO1Lyi6H_-A1OadQFYIO-wQEv0VXFj?usp=sharing which will lead to a Google Drive where our files are uploaded in its entirety.

FPGA Performance Characterisation

To characterise the performance of our FPGA, we measured the pulses produced by our FPGA with an oscilloscope (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals, and/or the frequency of the clock signals (which can be adjusted in integer multiples of the clock oscillator), we can obtain different performances (in terms of pulse widths and frequencies) of our pulses.
 
 
=====Best Overall Performance=====

The best overall performance was obtained when the phase difference between the clock signals was set at 11.25 degrees while the frequency of the clock signal is 150MHZ. We obtained a pulse width of 637ps at a frequency of 150MHZ.

[[File:d11.25f150_Best_Performance.png|600px]]

Unfortunately, pushing the FPGA further, we were unable to obtain narrower pulses with that higher frequencies.

[[File:D10f200 Too High Frequency For Pulse Width.png||600px]]

=====Highest Frequency=====

The best frequency performance was obtained when the phase difference between the clock signals was set at 15 degrees while the frequency of the clock signal is 200MHZ. We obtained a pulse width of 746 ps at a frequency of 200MHZ.

[[File:D15f200 _Best _Frequency.png||600px]]

=====Results as a Function of Phase Difference=====

We recall from "Methods" that the way to obtain the pulses was to carve the pulses out from two clock signals. Theoretically, the pulse duration should increase with phase difference for the same frequency. When the phase difference between the clock signals were set at 9, 18 and 37.5 degrees and the frequency of the clock signal is 100MHZ, we obtained a pulse width of 805 ps, pulse width of 1.2 ns and pulse width of 2.27ns respectively.

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D18f100_Function_Of_Phase_Difference_2.png||600px]]

[[File:D37.5f100_Function_Of_Phase_Difference_3.png||600px]]

=====Different Configurations For The Same Pulse Width (Theoretically)=====

Theoretically, the pulse duration should remain the same if the phase difference and frequency were increased with the same multiple. The plots below feature such a set of measurements. Barring the fact that the increase was not in perfect multiples due to the limited step control of the phase difference as well as the different frequency response of the circuit, this phenomenon was more or less observed.

[[File:D3.37f50.png||600px]]

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D11.25f150_Best_Performance.png||600px]]

=====Summary Table=====

[[File:Table.png||600px]]

====Application====

While we have achieved our goal of creating a working Nanosecond Pulse Generator with our FPGA similar to the works of Zhu & Wang, it is important to recognise the fact that the pulses created by the FPGA belong to low-power pulse signals between 1.2-3.3V based on the specific I/O standard for the FPGA.

Amplification may be required for our FPGA to work with other devices. In this section, we designed an amplifier with the intention of amplifying our pulses up to 7.8V based on the following schematics.

[[File:Amplifier.png||400px]]

[[File:Amplifer_2.jpg||300px]]

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

Main Page

2021-04-30T09:17:56Z

Chua Rui Ming: /* A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) */

Project wiki for the Module QT5201U (Quantum control technology) - AY20/21S2

Welcome to the wiki project page. This will be the place for documenting projects. To be able to write something to this wiki, we need to create a user login manually. If you have not yet created an account, do let me know - Christian.

Deadline for the reports will be 30 April 23:59SGT!

==Project proposals==
===[[Wavemeter based on interferometer]]===
Basically, we are now trying to build a wavemeter based on Michelson interferometer. The goal is to measure laser with a wavelength from 1200nm to 1800nm which can be used for these lasers in our lab. This project consists of work about optics and electronic control. The control system is mainly implemented by using a Arduino UNO board and some basic circuits.

===[[Coincidence Time Measurement of Pulsed Lasers & "Useful" Applications]]===
Proof-of-concept experiment to show how one may use commonly-available materials to measure difference in laser path lengths to sub-millimeter precision with a copper target (TBC). This experiment is done using a 355nm, 120 MHz, 10ps pulsed laser. Upon showing that such a measurement is possible, we shall go on to explore some for-fun applications of this "technology" and see how far and precise we can get.

===[[Saturated Absorption Spectroscopy + Frequency Modulation Locking on the D2 line of Rubidium 87]]===
With a combination of the Saturation Spectroscopy and Frequency Modulation techniques, we aim at stabilizing the wavelength of a Diode Laser at approximately 780.246 nm which corresponds to the transition <math>5S_{1/2},F=2 \rightarrow 5P_{3/2},F=3</math> of 87Rb. Additionally we will implement in the experiment a Red Pitaya, which is a minicomputer capable of replacing things like an Oscilloscope, Function Generator and PID controller. Therefore reducing the space needed for the experiment.

===[[Control over the atomic spins within certain molecules by NMR technique]]===
NMR has been the workhorse for the experimental implementation of quantum protocols, allowing exquisite control of systems up to seven qubits in size. However, there exists some experimental limitations in terms of the cross-talk, coupled evolution, instrumental errors and so on.
Thanks to the current advanced pulse techniques, we can reduce these influences and extend this technique to a new stage that the experimental limits can be neglected. In this experiment, we try to use composite pulses to compensate RF field strength variations and frequency offsets.

===[[Optical control of TMDCs valley pseudospin qubits]]===
Quantum dots or single electron transistors, allow for individual control of single charge or spin. In addition, some semiconductor monolayers possess a sizeable direct bandgap of ≈1.5–2 eV in the optical range allowing electrostatic confinement and optical manipulation of carriers. Therefore, we try to adopt the method of this theoretical paper, and see if we can control single qubit or couple 2 qubits optically.

===[[A temperature-tunable etalon for optical telecommunication wavelength]]===
This project aims to build a Fabry-perot interferometer (also called Etalon) that works at the optical telecommunication wavelengths (1260nm-1625nm). This depicted etalon is made out of a single piece of polished silicon wafer with a thickness of about 100μm. The free spectral range (FSR) of the etalon can be adjusted by changing its thickness through temperature tuning. We will also explore the possibility of applying highly reflective (HR) coatings to the silicon wafer to achieve a high cavity finesse and a narrow transmission line-width.

===[[Microwave control of superconducting cavity and qubit]]===
This project aims to perform a trial pre-experiment based on the cQED architecture including simulation, calibration, microwave control pulse programming, and so on. The 3D superconducting cavity sample is anchored to the MXC flange inside the Bluefors dilution refrigerator to reach a temperature of around 10mK. On the other hand, the generation of microwave control pulses and the acquisition of output signals are handled by a QM quantum control device, connecting the sample via the control lines and the output lines accordingly. Hence, we can realize several bosonic states via cavity driving and qubit control.

===[[A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)]]===
Field Programmable Gate Arrays (FPGAs) are digital integrated circuits (ICs) that contain blocks of logic and interconnects which can be configured and reconfigured even after it is being deployed "in the field". This enables flexible tunability in the function of FPGA-based devices. We seek to realise the claims of Zhu & Wang (2015) to utilise the Phase-Locked Loop (PLL) module in FPGA to implement a nanosecond pulse generator with adjustable frequency and pulse width. Our circuit was designed with Quartus Prime.

==Material requests==
Please add stuff we should organize one way or the other here:
* more space
* cookies...

==Stuff to be covered in the lecture slots on Mondays (sometimes Tuesdays as well)==
Feel free to add topics or aspects to this list. At the moment, this is just a copy of the tentative syllabus:

{| class="wikitable"
!Date !! Topic !! Description

|-
| 18.1.2021
|[https://youtu.be/vDIOn2SHLJE Paraxial optics, part 1]
| rowspan = "2" | Optical systems often work with Gaussian beams. We cover practical design techniques like the ABCD matrix formalism for simple optical systems.
|-
| 19.1.2021
|[https://youtu.be/yO3JcuCOVoc Paraxial optics, part 2] (only first part of lecture)
|-
| 25.1.2021||[https://youtu.be/nNU1eEOaPdY Optical cavities, part 1] || Many optical techniques require to work with optical cavities. We cover how to design them, and how to couple light into very basic devices. This lecture covered some theory basics.
|-
| 26.1.2021||[https://youtu.be/ekfhUi2JjFM Optical cavities, part 2]|| Some more aspects of optical cavities, and dielectric coatings for mirrors and such

|-
| 1.2.2021||[https://youtu.be/h2LeznCpPTk Optical fiber technology] || Some properties of optical fibers as the most common optical waveguide are covered, including optical mode spectrum, dispersion and transmission properties.

|-
| 8.2.2021||[https://youtu.be/xblN-KzMz0Y Optical modulators, part 1]
| rowspan = "2" | Many optical modulation techniques require rely on devices or materials where optical properties can be changed electrically; we cover accousto-optical and electro-optical devices, as well as liquid crystal systems.
|-
| 9.2.2021||[https://youtu.be/WfP5mahZrWU Optical modulators, part 2]

|-
| 15.2.2021
|[https://youtu.be/m_F4DOHMNeU Homodyne detection techniques] || Measurement of optical fields in many continuous variable scenarios require knowledge of optical homodyning and heterodyning techniques. These techniques, similar to their radiofrequency counterparts, rely on multiplying field amplitudes.

|-
| 1.3.2021
|[https://youtu.be/YkVlxxucLuA Frequency control of laser systems, part 1]
| rowspan="2" |Many laser systems in quantum technologies require to have a well-defined frequency relationship with atomic transitions or solid state qubits. We cover typical techniques how laser systems can be controlled to a high enough accuracy, utilizing spectroscopy techniques and control systems.
|-
| 2.3.2021
|[https://youtu.be/72aVZwI4BHU Frequency control of laser systems, part 2]

|-
| 8.3.2021
|[https://youtu.be/jolUa_EGZEs Interface to computers]
| High level interfacing between computers and electronic hardware: Standard device languages; some serial protocols, some aspects of microcontrollers and FPGAs

|-
| 15.3.2021
|[https://youtu.be/1S0EAnooQMc Pulses in quantum control]
| Many quantum systems require short control pulses, either in form of optical pulses or radiofrequency pulses. This covers how they are used, and present a few techniques to generate such control pulses

|-
| 22.3.2021
|[https://youtu.be/PHx-da7RLE8 High voltage techniques]
| Working with high voltages requires a spectrum of techniques that is differing from more conventional electronics. A few aspects (field emission, dielectric strength, specific components) are covered.

|-
|12.4.2021
|[https://youtu.be/K0U9ySRyvjs Control loops]
| Many experimental activities in controlling quantum systems require the control of classical systems, like the temperature stabilization of some device, or the frequency stabilization of a laser. This lecture gives a brief overview of some simple control concepts.

|-
| ||Practical aspects of superconducting systems || We cover different materials, transition temperatures, temperature measurement techniques and thermal insulation / conduction techniques.

|}

== Getting started ==
Consult the [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide] for information on using the wiki software.
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* Math can be entered in LaTeX style: <code><nowiki><math>r^2=\sqrt{x^2+y^2}</math></nowiki></code> renders as <math>r^2=\sqrt{x^2+y^2}</math>
* Should you miss any module or functionality of this wiki, please contact me (Christian Kurtsiefer).

Main Page

2021-04-30T09:15:54Z

Chua Rui Ming: /* A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) */

Project wiki for the Module QT5201U (Quantum control technology) - AY20/21S2

Welcome to the wiki project page. This will be the place for documenting projects. To be able to write something to this wiki, we need to create a user login manually. If you have not yet created an account, do let me know - Christian.

Deadline for the reports will be 30 April 23:59SGT!

==Project proposals==
===[[Wavemeter based on interferometer]]===
Basically, we are now trying to build a wavemeter based on Michelson interferometer. The goal is to measure laser with a wavelength from 1200nm to 1800nm which can be used for these lasers in our lab. This project consists of work about optics and electronic control. The control system is mainly implemented by using a Arduino UNO board and some basic circuits.

===[[Coincidence Time Measurement of Pulsed Lasers & "Useful" Applications]]===
Proof-of-concept experiment to show how one may use commonly-available materials to measure difference in laser path lengths to sub-millimeter precision with a copper target (TBC). This experiment is done using a 355nm, 120 MHz, 10ps pulsed laser. Upon showing that such a measurement is possible, we shall go on to explore some for-fun applications of this "technology" and see how far and precise we can get.

===[[Saturated Absorption Spectroscopy + Frequency Modulation Locking on the D2 line of Rubidium 87]]===
With a combination of the Saturation Spectroscopy and Frequency Modulation techniques, we aim at stabilizing the wavelength of a Diode Laser at approximately 780.246 nm which corresponds to the transition <math>5S_{1/2},F=2 \rightarrow 5P_{3/2},F=3</math> of 87Rb. Additionally we will implement in the experiment a Red Pitaya, which is a minicomputer capable of replacing things like an Oscilloscope, Function Generator and PID controller. Therefore reducing the space needed for the experiment.

===[[Control over the atomic spins within certain molecules by NMR technique]]===
NMR has been the workhorse for the experimental implementation of quantum protocols, allowing exquisite control of systems up to seven qubits in size. However, there exists some experimental limitations in terms of the cross-talk, coupled evolution, instrumental errors and so on.
Thanks to the current advanced pulse techniques, we can reduce these influences and extend this technique to a new stage that the experimental limits can be neglected. In this experiment, we try to use composite pulses to compensate RF field strength variations and frequency offsets.

===[[Optical control of TMDCs valley pseudospin qubits]]===
Quantum dots or single electron transistors, allow for individual control of single charge or spin. In addition, some semiconductor monolayers possess a sizeable direct bandgap of ≈1.5–2 eV in the optical range allowing electrostatic confinement and optical manipulation of carriers. Therefore, we try to adopt the method of this theoretical paper, and see if we can control single qubit or couple 2 qubits optically.

===[[A temperature-tunable etalon for optical telecommunication wavelength]]===
This project aims to build a Fabry-perot interferometer (also called Etalon) that works at the optical telecommunication wavelengths (1260nm-1625nm). This depicted etalon is made out of a single piece of polished silicon wafer with a thickness of about 100μm. The free spectral range (FSR) of the etalon can be adjusted by changing its thickness through temperature tuning. We will also explore the possibility of applying highly reflective (HR) coatings to the silicon wafer to achieve a high cavity finesse and a narrow transmission line-width.

===[[Microwave control of superconducting cavity and qubit]]===
This project aims to perform a trial pre-experiment based on the cQED architecture including simulation, calibration, microwave control pulse programming, and so on. The 3D superconducting cavity sample is anchored to the MXC flange inside the Bluefors dilution refrigerator to reach a temperature of around 10mK. On the other hand, the generation of microwave control pulses and the acquisition of output signals are handled by a QM quantum control device, connecting the sample via the control lines and the output lines accordingly. Hence, we can realize several bosonic states via cavity driving and qubit control.

===[[A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)]]===
Field Programmable Gate Arrays (FPGAs) are digital integrated circuits (ICs) that contain blocks of logic and interconnects which can be configured and reconfigured even after it is being deployed "in the field". This enables flexible tunability in the function of FPGA-based devices. We seek to emulate (with tweaks) the works of Zhu & Wang (2015) to utilise the Phase-Locked Loop (PLL) module in FPGA to implement a nanosecond pulse generator with adjustable frequency and pulse width. Our circuit was designed with Quartus Prime.

==Material requests==
Please add stuff we should organize one way or the other here:
* more space
* cookies...

==Stuff to be covered in the lecture slots on Mondays (sometimes Tuesdays as well)==
Feel free to add topics or aspects to this list. At the moment, this is just a copy of the tentative syllabus:

{| class="wikitable"
!Date !! Topic !! Description

|-
| 18.1.2021
|[https://youtu.be/vDIOn2SHLJE Paraxial optics, part 1]
| rowspan = "2" | Optical systems often work with Gaussian beams. We cover practical design techniques like the ABCD matrix formalism for simple optical systems.
|-
| 19.1.2021
|[https://youtu.be/yO3JcuCOVoc Paraxial optics, part 2] (only first part of lecture)
|-
| 25.1.2021||[https://youtu.be/nNU1eEOaPdY Optical cavities, part 1] || Many optical techniques require to work with optical cavities. We cover how to design them, and how to couple light into very basic devices. This lecture covered some theory basics.
|-
| 26.1.2021||[https://youtu.be/ekfhUi2JjFM Optical cavities, part 2]|| Some more aspects of optical cavities, and dielectric coatings for mirrors and such

|-
| 1.2.2021||[https://youtu.be/h2LeznCpPTk Optical fiber technology] || Some properties of optical fibers as the most common optical waveguide are covered, including optical mode spectrum, dispersion and transmission properties.

|-
| 8.2.2021||[https://youtu.be/xblN-KzMz0Y Optical modulators, part 1]
| rowspan = "2" | Many optical modulation techniques require rely on devices or materials where optical properties can be changed electrically; we cover accousto-optical and electro-optical devices, as well as liquid crystal systems.
|-
| 9.2.2021||[https://youtu.be/WfP5mahZrWU Optical modulators, part 2]

|-
| 15.2.2021
|[https://youtu.be/m_F4DOHMNeU Homodyne detection techniques] || Measurement of optical fields in many continuous variable scenarios require knowledge of optical homodyning and heterodyning techniques. These techniques, similar to their radiofrequency counterparts, rely on multiplying field amplitudes.

|-
| 1.3.2021
|[https://youtu.be/YkVlxxucLuA Frequency control of laser systems, part 1]
| rowspan="2" |Many laser systems in quantum technologies require to have a well-defined frequency relationship with atomic transitions or solid state qubits. We cover typical techniques how laser systems can be controlled to a high enough accuracy, utilizing spectroscopy techniques and control systems.
|-
| 2.3.2021
|[https://youtu.be/72aVZwI4BHU Frequency control of laser systems, part 2]

|-
| 8.3.2021
|[https://youtu.be/jolUa_EGZEs Interface to computers]
| High level interfacing between computers and electronic hardware: Standard device languages; some serial protocols, some aspects of microcontrollers and FPGAs

|-
| 15.3.2021
|[https://youtu.be/1S0EAnooQMc Pulses in quantum control]
| Many quantum systems require short control pulses, either in form of optical pulses or radiofrequency pulses. This covers how they are used, and present a few techniques to generate such control pulses

|-
| 22.3.2021
|[https://youtu.be/PHx-da7RLE8 High voltage techniques]
| Working with high voltages requires a spectrum of techniques that is differing from more conventional electronics. A few aspects (field emission, dielectric strength, specific components) are covered.

|-
|12.4.2021
|[https://youtu.be/K0U9ySRyvjs Control loops]
| Many experimental activities in controlling quantum systems require the control of classical systems, like the temperature stabilization of some device, or the frequency stabilization of a laser. This lecture gives a brief overview of some simple control concepts.

|-
| ||Practical aspects of superconducting systems || We cover different materials, transition temperatures, temperature measurement techniques and thermal insulation / conduction techniques.

|}

== Getting started ==
Consult the [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide] for information on using the wiki software.
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* Math can be entered in LaTeX style: <code><nowiki><math>r^2=\sqrt{x^2+y^2}</math></nowiki></code> renders as <math>r^2=\sqrt{x^2+y^2}</math>
* Should you miss any module or functionality of this wiki, please contact me (Christian Kurtsiefer).

Main Page

2021-04-30T09:15:05Z

Chua Rui Ming: /* A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) */

Project wiki for the Module QT5201U (Quantum control technology) - AY20/21S2

Welcome to the wiki project page. This will be the place for documenting projects. To be able to write something to this wiki, we need to create a user login manually. If you have not yet created an account, do let me know - Christian.

Deadline for the reports will be 30 April 23:59SGT!

==Project proposals==
===[[Wavemeter based on interferometer]]===
Basically, we are now trying to build a wavemeter based on Michelson interferometer. The goal is to measure laser with a wavelength from 1200nm to 1800nm which can be used for these lasers in our lab. This project consists of work about optics and electronic control. The control system is mainly implemented by using a Arduino UNO board and some basic circuits.

===[[Coincidence Time Measurement of Pulsed Lasers & "Useful" Applications]]===
Proof-of-concept experiment to show how one may use commonly-available materials to measure difference in laser path lengths to sub-millimeter precision with a copper target (TBC). This experiment is done using a 355nm, 120 MHz, 10ps pulsed laser. Upon showing that such a measurement is possible, we shall go on to explore some for-fun applications of this "technology" and see how far and precise we can get.

===[[Saturated Absorption Spectroscopy + Frequency Modulation Locking on the D2 line of Rubidium 87]]===
With a combination of the Saturation Spectroscopy and Frequency Modulation techniques, we aim at stabilizing the wavelength of a Diode Laser at approximately 780.246 nm which corresponds to the transition <math>5S_{1/2},F=2 \rightarrow 5P_{3/2},F=3</math> of 87Rb. Additionally we will implement in the experiment a Red Pitaya, which is a minicomputer capable of replacing things like an Oscilloscope, Function Generator and PID controller. Therefore reducing the space needed for the experiment.

===[[Control over the atomic spins within certain molecules by NMR technique]]===
NMR has been the workhorse for the experimental implementation of quantum protocols, allowing exquisite control of systems up to seven qubits in size. However, there exists some experimental limitations in terms of the cross-talk, coupled evolution, instrumental errors and so on.
Thanks to the current advanced pulse techniques, we can reduce these influences and extend this technique to a new stage that the experimental limits can be neglected. In this experiment, we try to use composite pulses to compensate RF field strength variations and frequency offsets.

===[[Optical control of TMDCs valley pseudospin qubits]]===
Quantum dots or single electron transistors, allow for individual control of single charge or spin. In addition, some semiconductor monolayers possess a sizeable direct bandgap of ≈1.5–2 eV in the optical range allowing electrostatic confinement and optical manipulation of carriers. Therefore, we try to adopt the method of this theoretical paper, and see if we can control single qubit or couple 2 qubits optically.

===[[A temperature-tunable etalon for optical telecommunication wavelength]]===
This project aims to build a Fabry-perot interferometer (also called Etalon) that works at the optical telecommunication wavelengths (1260nm-1625nm). This depicted etalon is made out of a single piece of polished silicon wafer with a thickness of about 100μm. The free spectral range (FSR) of the etalon can be adjusted by changing its thickness through temperature tuning. We will also explore the possibility of applying highly reflective (HR) coatings to the silicon wafer to achieve a high cavity finesse and a narrow transmission line-width.

===[[Microwave control of superconducting cavity and qubit]]===
This project aims to perform a trial pre-experiment based on the cQED architecture including simulation, calibration, microwave control pulse programming, and so on. The 3D superconducting cavity sample is anchored to the MXC flange inside the Bluefors dilution refrigerator to reach a temperature of around 10mK. On the other hand, the generation of microwave control pulses and the acquisition of output signals are handled by a QM quantum control device, connecting the sample via the control lines and the output lines accordingly. Hence, we can realize several bosonic states via cavity driving and qubit control.

===[[A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)]]===
Field Programmable Gate Arrays (FPGAs) are digital integrated circuits (ICs) that contain blocks of logic and interconnects which can be configured and reconfigured even after it is being deployed "in the field". This enables flexible tunability in the function of FPGA-based devices. We seek to emulate (with tweaks) and realise the works of Zhu & Wang (2015) to utilise the Phase-Locked Loop (PLL) module in FPGA to implement a nanosecond pulse generator with adjustable frequency and pulse width. Our circuit was designed with Quartus Prime.

==Material requests==
Please add stuff we should organize one way or the other here:
* more space
* cookies...

==Stuff to be covered in the lecture slots on Mondays (sometimes Tuesdays as well)==
Feel free to add topics or aspects to this list. At the moment, this is just a copy of the tentative syllabus:

{| class="wikitable"
!Date !! Topic !! Description

|-
| 18.1.2021
|[https://youtu.be/vDIOn2SHLJE Paraxial optics, part 1]
| rowspan = "2" | Optical systems often work with Gaussian beams. We cover practical design techniques like the ABCD matrix formalism for simple optical systems.
|-
| 19.1.2021
|[https://youtu.be/yO3JcuCOVoc Paraxial optics, part 2] (only first part of lecture)
|-
| 25.1.2021||[https://youtu.be/nNU1eEOaPdY Optical cavities, part 1] || Many optical techniques require to work with optical cavities. We cover how to design them, and how to couple light into very basic devices. This lecture covered some theory basics.
|-
| 26.1.2021||[https://youtu.be/ekfhUi2JjFM Optical cavities, part 2]|| Some more aspects of optical cavities, and dielectric coatings for mirrors and such

|-
| 1.2.2021||[https://youtu.be/h2LeznCpPTk Optical fiber technology] || Some properties of optical fibers as the most common optical waveguide are covered, including optical mode spectrum, dispersion and transmission properties.

|-
| 8.2.2021||[https://youtu.be/xblN-KzMz0Y Optical modulators, part 1]
| rowspan = "2" | Many optical modulation techniques require rely on devices or materials where optical properties can be changed electrically; we cover accousto-optical and electro-optical devices, as well as liquid crystal systems.
|-
| 9.2.2021||[https://youtu.be/WfP5mahZrWU Optical modulators, part 2]

|-
| 15.2.2021
|[https://youtu.be/m_F4DOHMNeU Homodyne detection techniques] || Measurement of optical fields in many continuous variable scenarios require knowledge of optical homodyning and heterodyning techniques. These techniques, similar to their radiofrequency counterparts, rely on multiplying field amplitudes.

|-
| 1.3.2021
|[https://youtu.be/YkVlxxucLuA Frequency control of laser systems, part 1]
| rowspan="2" |Many laser systems in quantum technologies require to have a well-defined frequency relationship with atomic transitions or solid state qubits. We cover typical techniques how laser systems can be controlled to a high enough accuracy, utilizing spectroscopy techniques and control systems.
|-
| 2.3.2021
|[https://youtu.be/72aVZwI4BHU Frequency control of laser systems, part 2]

|-
| 8.3.2021
|[https://youtu.be/jolUa_EGZEs Interface to computers]
| High level interfacing between computers and electronic hardware: Standard device languages; some serial protocols, some aspects of microcontrollers and FPGAs

|-
| 15.3.2021
|[https://youtu.be/1S0EAnooQMc Pulses in quantum control]
| Many quantum systems require short control pulses, either in form of optical pulses or radiofrequency pulses. This covers how they are used, and present a few techniques to generate such control pulses

|-
| 22.3.2021
|[https://youtu.be/PHx-da7RLE8 High voltage techniques]
| Working with high voltages requires a spectrum of techniques that is differing from more conventional electronics. A few aspects (field emission, dielectric strength, specific components) are covered.

|-
|12.4.2021
|[https://youtu.be/K0U9ySRyvjs Control loops]
| Many experimental activities in controlling quantum systems require the control of classical systems, like the temperature stabilization of some device, or the frequency stabilization of a laser. This lecture gives a brief overview of some simple control concepts.

|-
| ||Practical aspects of superconducting systems || We cover different materials, transition temperatures, temperature measurement techniques and thermal insulation / conduction techniques.

|}

== Getting started ==
Consult the [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide] for information on using the wiki software.
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* Math can be entered in LaTeX style: <code><nowiki><math>r^2=\sqrt{x^2+y^2}</math></nowiki></code> renders as <math>r^2=\sqrt{x^2+y^2}</math>
* Should you miss any module or functionality of this wiki, please contact me (Christian Kurtsiefer).

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-30T09:07:34Z

Chua Rui Ming: /* Summary Table */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
=====Product=====

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

=====Architecture=====

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

=====Preview=====

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. There are two reasons for our choice: Firstly, this simplifies the problem. Secondly, this way, we obtain two pulses for every set of clock signals- At the front-end and tail-end of the first and second clock signals respectively:

<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


[[File:2-Figure3-2.png||350px]]

For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

=====FPGA Top Design=====

[[File:Top_Design.png|1200px]]

The bulk of our efforts went into the code to configure the Nanosecond Pulse Generator. The FPGA Top Design summarises the outcome of our efforts. Our efforts in its entirety could be found here https://drive.google.com/drive/folders/1weGO1Lyi6H_-A1OadQFYIO-wQEv0VXFj?usp=sharing which will lead to a Google Drive where our files are uploaded in its entirety.

FPGA Performance Characterisation

To characterise the performance of our FPGA, we measured the pulses produced by our FPGA with an oscilloscope (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals, and/or the frequency of the clock signals (which can be adjusted in integer multiples of the clock oscillator), we can obtain different performances (in terms of pulse widths and frequencies) of our pulses.
 
 
=====Best Overall Performance=====

The best overall performance was obtained when the phase difference between the clock signals was set at 11.25 degrees while the frequency of the clock signal is 150MHZ. We obtained a pulse width of 637ps at a frequency of 150MHZ.

[[File:d11.25f150_Best_Performance.png|600px]]

Unfortunately, pushing the FPGA further, we were unable to obtain narrower pulses with that higher frequencies.

[[File:D10f200 Too High Frequency For Pulse Width.png||600px]]

=====Highest Frequency=====

The best frequency performance was obtained when the phase difference between the clock signals was set at 15 degrees while the frequency of the clock signal is 200MHZ. We obtained a pulse width of 746 ps at a frequency of 200MHZ.

[[File:D15f200 _Best _Frequency.png||600px]]

=====Results as a Function of Phase Difference=====

We recall from "Methods" that the way to obtain the pulses was to carve the pulses out from two clock signals. Theoretically, the pulse duration should increase with phase difference for the same frequency. When the phase difference between the clock signals were set at 9, 18 and 37.5 degrees and the frequency of the clock signal is 100MHZ, we obtained a pulse width of 805 ps, pulse width of 1.2 ns and pulse width of 2.27ns respectively.

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D18f100_Function_Of_Phase_Difference_2.png||600px]]

[[File:D37.5f100_Function_Of_Phase_Difference_3.png||600px]]

=====Different Configurations For The Same Pulse Width (Theoretically)=====

Theoretically, the pulse duration should remain the same if the phase difference and frequency were increased with the same multiple. The plots below feature such a measurement.

[[File:D3.37f50.png||600px]]

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D11.25f150_Best_Performance.png||600px]]

=====Summary Table=====

[[File:Table.png||600px]]

====Application====

While we have achieved our goal of creating a working Nanosecond Pulse Generator with our FPGA similar to the works of Zhu & Wang, it is important to recognise the fact that the pulses created by the FPGA belong to low-power pulse signals between 1.2-3.3V based on the specific I/O standard for the FPGA.

Amplification may be required for our FPGA to work with other devices. In this section, we designed an amplifier with the intention of amplifying our pulses up to 7.8V based on the following schematics.

[[File:Amplifier.png||400px]]

[[File:Amplifer_2.jpg||300px]]

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

File:Table.png

2021-04-30T09:06:36Z

Chua Rui Ming:

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-30T09:05:17Z

Chua Rui Ming: /* Results */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
=====Product=====

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

=====Architecture=====

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

=====Preview=====

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. There are two reasons for our choice: Firstly, this simplifies the problem. Secondly, this way, we obtain two pulses for every set of clock signals- At the front-end and tail-end of the first and second clock signals respectively:

<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


[[File:2-Figure3-2.png||350px]]

For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

=====FPGA Top Design=====

[[File:Top_Design.png|1200px]]

The bulk of our efforts went into the code to configure the Nanosecond Pulse Generator. The FPGA Top Design summarises the outcome of our efforts. Our efforts in its entirety could be found here https://drive.google.com/drive/folders/1weGO1Lyi6H_-A1OadQFYIO-wQEv0VXFj?usp=sharing which will lead to a Google Drive where our files are uploaded in its entirety.

FPGA Performance Characterisation

To characterise the performance of our FPGA, we measured the pulses produced by our FPGA with an oscilloscope (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals, and/or the frequency of the clock signals (which can be adjusted in integer multiples of the clock oscillator), we can obtain different performances (in terms of pulse widths and frequencies) of our pulses.
 
 
=====Best Overall Performance=====

The best overall performance was obtained when the phase difference between the clock signals was set at 11.25 degrees while the frequency of the clock signal is 150MHZ. We obtained a pulse width of 637ps at a frequency of 150MHZ.

[[File:d11.25f150_Best_Performance.png|600px]]

Unfortunately, pushing the FPGA further, we were unable to obtain narrower pulses with that higher frequencies.

[[File:D10f200 Too High Frequency For Pulse Width.png||600px]]

=====Highest Frequency=====

The best frequency performance was obtained when the phase difference between the clock signals was set at 15 degrees while the frequency of the clock signal is 200MHZ. We obtained a pulse width of 746 ps at a frequency of 200MHZ.

[[File:D15f200 _Best _Frequency.png||600px]]

=====Results as a Function of Phase Difference=====

We recall from "Methods" that the way to obtain the pulses was to carve the pulses out from two clock signals. Theoretically, the pulse duration should increase with phase difference for the same frequency. When the phase difference between the clock signals were set at 9, 18 and 37.5 degrees and the frequency of the clock signal is 100MHZ, we obtained a pulse width of 805 ps, pulse width of 1.2 ns and pulse width of 2.27ns respectively.

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D18f100_Function_Of_Phase_Difference_2.png||600px]]

[[File:D37.5f100_Function_Of_Phase_Difference_3.png||600px]]

=====Different Configurations For The Same Pulse Width (Theoretically)=====

Theoretically, the pulse duration should remain the same if the phase difference and frequency were increased with the same multiple. The plots below feature such a measurement.

[[File:D3.37f50.png||600px]]

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D11.25f150_Best_Performance.png||600px]]

=====Summary Table=====

====Application====

While we have achieved our goal of creating a working Nanosecond Pulse Generator with our FPGA similar to the works of Zhu & Wang, it is important to recognise the fact that the pulses created by the FPGA belong to low-power pulse signals between 1.2-3.3V based on the specific I/O standard for the FPGA.

Amplification may be required for our FPGA to work with other devices. In this section, we designed an amplifier with the intention of amplifying our pulses up to 7.8V based on the following schematics.

[[File:Amplifier.png||400px]]

[[File:Amplifer_2.jpg||300px]]

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-30T09:03:16Z

Chua Rui Ming: /* Product */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
=====Product=====

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

=====Architecture=====

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

=====Preview=====

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. There are two reasons for our choice: Firstly, this simplifies the problem. Secondly, this way, we obtain two pulses for every set of clock signals- At the front-end and tail-end of the first and second clock signals respectively:

<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


[[File:2-Figure3-2.png||350px]]

For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

FPGA Top Design

[[File:Top_Design.png|1200px]]

The bulk of our efforts went into the code to configure the Nanosecond Pulse Generator. The FPGA Top Design summarises the outcome of our efforts. Our efforts in its entirety could be found here https://drive.google.com/drive/folders/1weGO1Lyi6H_-A1OadQFYIO-wQEv0VXFj?usp=sharing which will lead to a Google Drive where our files are uploaded in its entirety.

FPGA Performance Characterisation

To characterise the performance of our FPGA, we measured the pulses produced by our FPGA with an oscilloscope (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals, and/or the frequency of the clock signals (which can be adjusted in integer multiples of the clock oscillator), we can obtain different performances (in terms of pulse widths and frequencies) of our pulses.
 
 
1) Best Overall Performance

The best overall performance was obtained when the phase difference between the clock signals was set at 11.25 degrees while the frequency of the clock signal is 150MHZ. We obtained a pulse width of 637ps at a frequency of 150MHZ.

[[File:d11.25f150_Best_Performance.png|600px]]

Unfortunately, pushing the FPGA further, we were unable to obtain narrower pulses with that higher frequencies.

[[File:D10f200 Too High Frequency For Pulse Width.png||600px]]

2) Highest Frequency 

The best frequency performance was obtained when the phase difference between the clock signals was set at 15 degrees while the frequency of the clock signal is 200MHZ. We obtained a pulse width of 746 ps at a frequency of 200MHZ.

[[File:D15f200 _Best _Frequency.png||600px]]

3) Results as a Function of Phase Difference 

We recall from "Methods" that the way to obtain the pulses was to carve the pulses out from two clock signals. Theoretically, the pulse duration should increase with phase difference for the same frequency. When the phase difference between the clock signals were set at 9, 18 and 37.5 degrees and the frequency of the clock signal is 100MHZ, we obtained a pulse width of 805 ps, pulse width of 1.2 ns and pulse width of 2.27ns respectively.

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D18f100_Function_Of_Phase_Difference_2.png||600px]]

[[File:D37.5f100_Function_Of_Phase_Difference_3.png||600px]]

4) Different Configurations For The Same Pulse Width (Theoretically) 

Theoretically, the pulse duration should remain the same if the phase difference and frequency were increased with the same multiple. The plots below feature such a measurement.

[[File:D3.37f50.png||600px]]

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D11.25f150_Best_Performance.png||600px]]

Summary Table

====Application====

While we have achieved our goal of creating a working Nanosecond Pulse Generator with our FPGA similar to the works of Zhu & Wang, it is important to recognise the fact that the pulses created by the FPGA belong to low-power pulse signals between 1.2-3.3V based on the specific I/O standard for the FPGA.

Amplification may be required for our FPGA to work with other devices. In this section, we designed an amplifier with the intention of amplifying our pulses up to 7.8V based on the following schematics.

[[File:Amplifier.png||400px]]

[[File:Amplifer_2.jpg||300px]]

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-30T09:02:30Z

Chua Rui Ming: /* FPGA Specifications */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
=====Product=====

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

Architecture

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

Preview

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. There are two reasons for our choice: Firstly, this simplifies the problem. Secondly, this way, we obtain two pulses for every set of clock signals- At the front-end and tail-end of the first and second clock signals respectively:

<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


[[File:2-Figure3-2.png||350px]]

For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

FPGA Top Design

[[File:Top_Design.png|1200px]]

The bulk of our efforts went into the code to configure the Nanosecond Pulse Generator. The FPGA Top Design summarises the outcome of our efforts. Our efforts in its entirety could be found here https://drive.google.com/drive/folders/1weGO1Lyi6H_-A1OadQFYIO-wQEv0VXFj?usp=sharing which will lead to a Google Drive where our files are uploaded in its entirety.

FPGA Performance Characterisation

To characterise the performance of our FPGA, we measured the pulses produced by our FPGA with an oscilloscope (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals, and/or the frequency of the clock signals (which can be adjusted in integer multiples of the clock oscillator), we can obtain different performances (in terms of pulse widths and frequencies) of our pulses.
 
 
1) Best Overall Performance

The best overall performance was obtained when the phase difference between the clock signals was set at 11.25 degrees while the frequency of the clock signal is 150MHZ. We obtained a pulse width of 637ps at a frequency of 150MHZ.

[[File:d11.25f150_Best_Performance.png|600px]]

Unfortunately, pushing the FPGA further, we were unable to obtain narrower pulses with that higher frequencies.

[[File:D10f200 Too High Frequency For Pulse Width.png||600px]]

2) Highest Frequency 

The best frequency performance was obtained when the phase difference between the clock signals was set at 15 degrees while the frequency of the clock signal is 200MHZ. We obtained a pulse width of 746 ps at a frequency of 200MHZ.

[[File:D15f200 _Best _Frequency.png||600px]]

3) Results as a Function of Phase Difference 

We recall from "Methods" that the way to obtain the pulses was to carve the pulses out from two clock signals. Theoretically, the pulse duration should increase with phase difference for the same frequency. When the phase difference between the clock signals were set at 9, 18 and 37.5 degrees and the frequency of the clock signal is 100MHZ, we obtained a pulse width of 805 ps, pulse width of 1.2 ns and pulse width of 2.27ns respectively.

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D18f100_Function_Of_Phase_Difference_2.png||600px]]

[[File:D37.5f100_Function_Of_Phase_Difference_3.png||600px]]

4) Different Configurations For The Same Pulse Width (Theoretically) 

Theoretically, the pulse duration should remain the same if the phase difference and frequency were increased with the same multiple. The plots below feature such a measurement.

[[File:D3.37f50.png||600px]]

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D11.25f150_Best_Performance.png||600px]]

Summary Table

====Application====

While we have achieved our goal of creating a working Nanosecond Pulse Generator with our FPGA similar to the works of Zhu & Wang, it is important to recognise the fact that the pulses created by the FPGA belong to low-power pulse signals between 1.2-3.3V based on the specific I/O standard for the FPGA.

Amplification may be required for our FPGA to work with other devices. In this section, we designed an amplifier with the intention of amplifying our pulses up to 7.8V based on the following schematics.

[[File:Amplifier.png||400px]]

[[File:Amplifer_2.jpg||300px]]

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-29T10:38:09Z

Chua Rui Ming: /* Application */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
Product

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

Architecture

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

Preview

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. There are two reasons for our choice: Firstly, this simplifies the problem. Secondly, this way, we obtain two pulses for every set of clock signals- At the front-end and tail-end of the first and second clock signals respectively:

<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


[[File:2-Figure3-2.png||350px]]

For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

FPGA Top Design

[[File:Top_Design.png|1200px]]

The bulk of our efforts went into the code to configure the Nanosecond Pulse Generator. The FPGA Top Design summarises the outcome of our efforts. Our efforts in its entirety could be found here https://drive.google.com/drive/folders/1weGO1Lyi6H_-A1OadQFYIO-wQEv0VXFj?usp=sharing which will lead to a Google Drive where our files are uploaded in its entirety.

FPGA Performance Characterisation

To characterise the performance of our FPGA, we measured the pulses produced by our FPGA with an oscilloscope (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals, and/or the frequency of the clock signals (which can be adjusted in integer multiples of the clock oscillator), we can obtain different performances (in terms of pulse widths and frequencies) of our pulses.
 
 
1) Best Overall Performance

The best overall performance was obtained when the phase difference between the clock signals was set at 11.25 degrees while the frequency of the clock signal is 150MHZ. We obtained a pulse width of 637ps at a frequency of 150MHZ.

[[File:d11.25f150_Best_Performance.png|600px]]

Unfortunately, pushing the FPGA further, we were unable to obtain narrower pulses with that higher frequencies.

[[File:D10f200 Too High Frequency For Pulse Width.png||600px]]

2) Highest Frequency 

The best frequency performance was obtained when the phase difference between the clock signals was set at 15 degrees while the frequency of the clock signal is 200MHZ. We obtained a pulse width of 746 ps at a frequency of 200MHZ.

[[File:D15f200 _Best _Frequency.png||600px]]

3) Results as a Function of Phase Difference 

We recall from "Methods" that the way to obtain the pulses was to carve the pulses out from two clock signals. Theoretically, the pulse duration should increase with phase difference for the same frequency. When the phase difference between the clock signals were set at 9, 18 and 37.5 degrees and the frequency of the clock signal is 100MHZ, we obtained a pulse width of 805 ps, pulse width of 1.2 ns and pulse width of 2.27ns respectively.

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D18f100_Function_Of_Phase_Difference_2.png||600px]]

[[File:D37.5f100_Function_Of_Phase_Difference_3.png||600px]]

4) Different Configurations For The Same Pulse Width (Theoretically) 

Theoretically, the pulse duration should remain the same if the phase difference and frequency were increased with the same multiple. The plots below feature such a measurement.

[[File:D3.37f50.png||600px]]

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D11.25f150_Best_Performance.png||600px]]

Summary Table

====Application====

While we have achieved our goal of creating a working Nanosecond Pulse Generator with our FPGA similar to the works of Zhu & Wang, it is important to recognise the fact that the pulses created by the FPGA belong to low-power pulse signals between 1.2-3.3V based on the specific I/O standard for the FPGA.

Amplification may be required for our FPGA to work with other devices. In this section, we designed an amplifier with the intention of amplifying our pulses up to 7.8V based on the following schematics.

[[File:Amplifier.png||400px]]

[[File:Amplifer_2.jpg||300px]]

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

File:Amplifer 2.jpg

2021-04-29T10:22:56Z

Chua Rui Ming:

File:Amplifier.png

2021-04-29T10:21:56Z

Chua Rui Ming:

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-29T10:19:07Z

Chua Rui Ming: /* Results */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
Product

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

Architecture

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

Preview

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. There are two reasons for our choice: Firstly, this simplifies the problem. Secondly, this way, we obtain two pulses for every set of clock signals- At the front-end and tail-end of the first and second clock signals respectively:

<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


[[File:2-Figure3-2.png||350px]]

For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

FPGA Top Design

[[File:Top_Design.png|1200px]]

The bulk of our efforts went into the code to configure the Nanosecond Pulse Generator. The FPGA Top Design summarises the outcome of our efforts. Our efforts in its entirety could be found here https://drive.google.com/drive/folders/1weGO1Lyi6H_-A1OadQFYIO-wQEv0VXFj?usp=sharing which will lead to a Google Drive where our files are uploaded in its entirety.

FPGA Performance Characterisation

To characterise the performance of our FPGA, we measured the pulses produced by our FPGA with an oscilloscope (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals, and/or the frequency of the clock signals (which can be adjusted in integer multiples of the clock oscillator), we can obtain different performances (in terms of pulse widths and frequencies) of our pulses.
 
 
1) Best Overall Performance

The best overall performance was obtained when the phase difference between the clock signals was set at 11.25 degrees while the frequency of the clock signal is 150MHZ. We obtained a pulse width of 637ps at a frequency of 150MHZ.

[[File:d11.25f150_Best_Performance.png|600px]]

Unfortunately, pushing the FPGA further, we were unable to obtain narrower pulses with that higher frequencies.

[[File:D10f200 Too High Frequency For Pulse Width.png||600px]]

2) Highest Frequency 

The best frequency performance was obtained when the phase difference between the clock signals was set at 15 degrees while the frequency of the clock signal is 200MHZ. We obtained a pulse width of 746 ps at a frequency of 200MHZ.

[[File:D15f200 _Best _Frequency.png||600px]]

3) Results as a Function of Phase Difference 

We recall from "Methods" that the way to obtain the pulses was to carve the pulses out from two clock signals. Theoretically, the pulse duration should increase with phase difference for the same frequency. When the phase difference between the clock signals were set at 9, 18 and 37.5 degrees and the frequency of the clock signal is 100MHZ, we obtained a pulse width of 805 ps, pulse width of 1.2 ns and pulse width of 2.27ns respectively.

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D18f100_Function_Of_Phase_Difference_2.png||600px]]

[[File:D37.5f100_Function_Of_Phase_Difference_3.png||600px]]

4) Different Configurations For The Same Pulse Width (Theoretically) 

Theoretically, the pulse duration should remain the same if the phase difference and frequency were increased with the same multiple. The plots below feature such a measurement.

[[File:D3.37f50.png||600px]]

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D11.25f150_Best_Performance.png||600px]]

Summary Table

====Application====

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

File:D3.37f50.png

2021-04-29T10:00:32Z

Chua Rui Ming:

File:D37.5f100 Function Of Phase Difference 3.png

2021-04-29T09:51:49Z

Chua Rui Ming:

File:D18f100 Function Of Phase Difference 2.png

2021-04-29T09:51:01Z

Chua Rui Ming:

File:D9f100 Function Of Phase Difference 1.png

2021-04-29T09:50:13Z

Chua Rui Ming: Function of Frequency

== Summary ==
Function of Frequency

File:D15f200 Best Frequency.png

2021-04-29T09:36:31Z

Chua Rui Ming: Best Frequency

== Summary ==
Best Frequency

File:D10f200 Too High Frequency For Pulse Width.png

2021-04-29T09:21:57Z

Chua Rui Ming: Tried to maintain the narrow pulse width while pushing the pulse frequency up. Limit was reached.

== Summary ==
Tried to maintain the narrow pulse width while pushing the pulse frequency up. Limit was reached.

File:D11.25f150 Best Performance.png

2021-04-29T09:13:18Z

Chua Rui Ming: Best Performance of our FPGA!

== Summary ==
Best Performance of our FPGA!

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-29T08:40:38Z

Chua Rui Ming: /* Results */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
Product

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

Architecture

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

Preview

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. There are two reasons for our choice: Firstly, this simplifies the problem. Secondly, this way, we obtain two pulses for every set of clock signals- At the front-end and tail-end of the first and second clock signals respectively:

<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


[[File:2-Figure3-2.png||350px]]

For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

FPGA Top Design

[[File:Top_Design.png|1200px]]

The bulk of our efforts went into the code to configure the Nanosecond Pulse Generator. The FPGA Top Design summarises the outcome of our efforts. Our efforts in its entirety could be found here https://drive.google.com/drive/folders/1weGO1Lyi6H_-A1OadQFYIO-wQEv0VXFj?usp=sharing which will lead to a Google Drive where our files are uploaded in its entirety.

FPGA Performance Characterisation

To characterise the performance of our FPGA, we measured the pulses produced by our FPGA (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals or the frequency of the clock signals we can obtain different performances (in terms of different pulse widths and frequencies) of our FPGA.

Hence, we characterised the performance of our FPGA as a function of the Phase Difference and Clock Frequencies.

1) Pulses as a function of Phase Difference

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

2) Pulses as a function of Frequency

The clock frequency may be adjusted in integer multiples of the clock oscillator (refer to FPGA Architecture).

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

Summary Table

====Application====

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-29T06:17:01Z

Chua Rui Ming: /* Results */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
Product

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

Architecture

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

Preview

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. There are two reasons for our choice: Firstly, this simplifies the problem. Secondly, this way, we obtain two pulses for every set of clock signals- At the front-end and tail-end of the first and second clock signals respectively:

<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


[[File:2-Figure3-2.png||350px]]

For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

FPGA Top Design

[[File:Top_Design.png|1200px]]

The bulk of our efforts went into the code to configure the Nanosecond Pulse Generator. The FPGA Top Design summarises the outcome of our efforts.

Our efforts in its entirety could be found this <a href="https://drive.google.com/drive/folders/1weGO1Lyi6H_-A1OadQFYIO-wQEv0VXFj?usp=sharing">Test</a> which will lead to a Google Drive where our files are uploaded in its entirety

In Zhu & Wang's paper

To characterise the performance of our FPGA, we measured the pulses produced by our FPGA (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals or the frequency of the clock signals we can obtain different performances (in terms of different pulse width and frequencies) of our FPGA. Hence, we characterised the performance of our FPGA as a function of the Phase Difference and as a function of Clock Frequency.

Pulses as a function of Phase Difference

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

Pulses as a function of Frequency

The clock frequency may be adjusted in integer multiples of the clock oscillator (refer to FPGA Architecture).

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

Summary Table

====Application====

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-29T05:55:54Z

Chua Rui Ming: /* Results */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
Product

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

Architecture

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

Preview

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. There are two reasons for our choice: Firstly, this simplifies the problem. Secondly, this way, we obtain two pulses for every set of clock signals- At the front-end and tail-end of the first and second clock signals respectively:

<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


[[File:2-Figure3-2.png||350px]]

For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

FPGA Top Design

[[File:Top_Design.png|1200px]]

The bulk of our efforts went into the code to configure the Nanosecond Pulse Generator. The FPGA Top Design summarises the outcome of our efforts.

Our efforts in its entirety could be found this https://drive.google.com/drive/folders/1weGO1Lyi6H_-A1OadQFYIO-wQEv0VXFj?usp=sharing which will lead to a Google Drive where our files are uploaded in its entirety

In Zhu & Wang's paper

To characterise the performance of our FPGA, we measured the pulses produced by our FPGA (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals or the frequency of the clock signals we can obtain different performances (in terms of different pulse width and frequencies) of our FPGA. Hence, we characterised the performance of our FPGA as a function of the Phase Difference and as a function of Clock Frequency.

Pulses as a function of Phase Difference

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

Pulses as a function of Frequency

The clock frequency may be adjusted in integer multiples of the clock oscillator (refer to FPGA Architecture).

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

Summary Table

====Application====

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

File:Top Design.png

2021-04-29T05:26:42Z

Chua Rui Ming: Chua Rui Ming uploaded a new version of File:Top Design.png

== Summary ==
FPGA Top Design

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-29T05:11:22Z

Chua Rui Ming: /* Results */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
Product

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

Architecture

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

Preview

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. There are two reasons for our choice: Firstly, this simplifies the problem. Secondly, this way, we obtain two pulses for every set of clock signals- At the front-end and tail-end of the first and second clock signals respectively:

<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


[[File:2-Figure3-2.png||350px]]

For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

FPGA Top Design

[[File:Top_Design.png|800px]]

The FPGA Top Design summarises the outcome of our code behind the design of our FPGA. To characterise the performance of our FPGA, we measured the pulses produced by our FPGA (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals or the frequency of the clock signals we can obtain different performances (in terms of different pulse width and frequencies) of our FPGA. Hence, we characterised the performance of our FPGA as a function of the Phase Difference and as a function of Clock Frequency.

Pulses as a function of Phase Difference

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

Pulses as a function of Frequency

The clock frequency may be adjusted in integer multiples of the clock oscillator (refer to FPGA Architecture).

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

Summary Table

====Application====

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-29T05:08:52Z

Chua Rui Ming: /* Methods */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
Product

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

Architecture

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

Preview

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. There are two reasons for our choice: Firstly, this simplifies the problem. Secondly, this way, we obtain two pulses for every set of clock signals- At the front-end and tail-end of the first and second clock signals respectively:

<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


[[File:2-Figure3-2.png||350px]]

For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

FPGA Top Design

[[File:Insert Image Here||300px]]

The FPGA Top Design summarises the outcome of our code behind the design of our FPGA. To characterise the performance of our FPGA, we measured the pulses produced by our FPGA (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals or the frequency of the clock signals we can obtain different performances (in terms of different pulse width and frequencies) of our FPGA. Hence, we characterised the performance of our FPGA as a function of the Phase Difference and as a function of Clock Frequency.

Pulses as a function of Phase Difference

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

Pulses as a function of Frequency

The clock frequency may be adjusted in integer multiples of the clock oscillator (refer to FPGA Architecture).

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

Summary Table

====Application====

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-29T05:08:08Z

Chua Rui Ming: /* Methods */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
Product

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

Architecture

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

Preview

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. There are two reasons for our choice: Firstly, this simplifies the problem. Secondly, this way we obtain two pulses for every set of clock signals.

This produces two rather than one narrow pulse for every pair of clock signals- At the front-end and tail-end of the first and second clock signals respectively:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


[[File:2-Figure3-2.png||350px]]

For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

FPGA Top Design

[[File:Insert Image Here||300px]]

The FPGA Top Design summarises the outcome of our code behind the design of our FPGA. To characterise the performance of our FPGA, we measured the pulses produced by our FPGA (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals or the frequency of the clock signals we can obtain different performances (in terms of different pulse width and frequencies) of our FPGA. Hence, we characterised the performance of our FPGA as a function of the Phase Difference and as a function of Clock Frequency.

Pulses as a function of Phase Difference

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

Pulses as a function of Frequency

The clock frequency may be adjusted in integer multiples of the clock oscillator (refer to FPGA Architecture).

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

Summary Table

====Application====

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

File:Top Design.png

2021-04-29T05:05:05Z

Chua Rui Ming: FPGA Top Design

== Summary ==
FPGA Top Design

Main Page

2021-04-28T19:01:53Z

Chua Rui Ming: /* A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) */

Project wiki for the Module QT5201U (Quantum control technology) - AY20/21S2

Welcome to the wiki project page. This will be the place for documenting projects. To be able to write something to this wiki, we need to create a user login manually. If you have not yet created an account, do let me know - Christian.

Deadline for the reports will be 30 April 23:59SGT!

==Project proposals==
===[[Wavemeter based on interferometer]]===
Basically, we are now trying to build a wavemeter based on Michelson interferometer. The goal is to measure laser with a wavelength from 1200nm to 1800nm which can be used for these lasers in our lab. This project consists of work about optics and electronic control. The control system is mainly implemented by using a Arduino UNO board and some basic circuits.

===[[Coincidence Time Measurement of Pulsed Lasers & "Useful" Applications]]===
Proof-of-concept experiment to show how one may use commonly-available materials to measure difference in laser path lengths to sub-millimeter precision with a copper target (TBC). This experiment is done using a 355nm, 120 MHz, 10ps pulsed laser. Upon showing that such a measurement is possible, we shall go on to explore some for-fun applications of this "technology" and see how far and precise we can get.

===[[Saturated Absorption Spectroscopy + Frequency Modulation Locking on the D2 line of Rubidium 87]]===
With a combination of the Saturation Spectroscopy and Frequency Modulation techniques, we aim at stabilizing the wavelength of a Diode Laser at approximately 780.241 nm which corresponds to the transition <math>5S_{1/2} \rightarrow 5P_{3/2}</math> (also known as D2 line) of Rubidium 87. Additionally we will implement in the experiment a Red Pitaya, which is a minicomputer capable of replacing things like an Oscilloscope, Function Generator and PID controller. Therefore reducing the space needed for the experiment.

===[[Control over the atomic spins within certain molecules by NMR technique]]===
NMR has been the workhorse for the experimental implementation of quantum protocols, allowing exquisite control of systems up to seven qubits in size. However, there exists some experimental limitations in terms of the cross-talk, coupled evolution, instrumental errors and so on.
Thanks to the current advanced pulse techniques, we can reduce these influences and extend this technique to a new stage that the experimental limits can be neglected. In this experiment, we try to use composite pulses to compensate RF field strength variations and frequency offsets.

===[[Optical control of TMDCs valley pseudospin qubits]]===
Quantum dots or single electron transistors, allow for individual control of single charge or spin. In addition, some semiconductor monolayers possess a sizeable direct bandgap of ≈1.5–2 eV in the optical range allowing electrostatic confinement and optical manipulation of carriers. Therefore, we try to adopt the method of this theoretical paper, and see if we can control single qubit or couple 2 qubits optically.

===[[A temperature-tunable etalon for optical telecommunication wavelength]]===
This project aims to build a Fabry-perot interferometer (also called Etalon) that works at the optical telecommunication wavelengths (1260nm-1625nm). This depicted etalon is made out of a single piece of polished silicon wafer with a thickness of about 100μm. The free spectral range (FSR) of the etalon can be adjusted by changing its thickness through temperature tuning. We will also explore the possibility of applying highly reflective (HR) coatings to the silicon wafer to achieve a high cavity finesse and a narrow transmission line-width.

===[[Microwave control of superconducting cavity and qubit]]===
This project aims to perform a trial pre-experiment based on the cQED architecture including simulation, calibration, microwave control pulse programming, and so on. The 3D superconducting cavity sample is anchored to the MXC flange inside the Bluefors dilution refrigerator to reach a temperature of around 10mK. On the other hand, the generation of microwave control pulses and the acquisition of output signals are handled by a QM quantum control device, connecting the sample via the control lines and the output lines accordingly. Hence, we can realize several bosonic states via cavity driving and qubit control.

===[[A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)]]===
Field Programmable Gate Arrays (FPGAs) are digital integrated circuits (ICs) that contain blocks of logic and interconnects which can be configured and reconfigured even after it is being deployed "in the field". This enables flexible tunability in the function of FPGA-based devices. We seek to emulate (with tweaks) the works of Zhu & Wang (2015) to utilise the Phase-Locked Loop (PLL) module in FPGA to implement a nanosecond pulse generator with adjustable frequency and pulse width. Our circuit was designed with Quartus Prime.

==Material requests==
Please add stuff we should organize one way or the other here:
* more space
* cookies...

==Stuff to be covered in the lecture slots on Mondays (sometimes Tuesdays as well)==
Feel free to add topics or aspects to this list. At the moment, this is just a copy of the tentative syllabus:

{| class="wikitable"
!Date !! Topic !! Description

|-
| 18.1.2021
|[https://youtu.be/vDIOn2SHLJE Paraxial optics, part 1]
| rowspan = "2" | Optical systems often work with Gaussian beams. We cover practical design techniques like the ABCD matrix formalism for simple optical systems.
|-
| 19.1.2021
|[https://youtu.be/yO3JcuCOVoc Paraxial optics, part 2] (only first part of lecture)
|-
| 25.1.2021||[https://youtu.be/nNU1eEOaPdY Optical cavities, part 1] || Many optical techniques require to work with optical cavities. We cover how to design them, and how to couple light into very basic devices. This lecture covered some theory basics.
|-
| 26.1.2021||[https://youtu.be/ekfhUi2JjFM Optical cavities, part 2]|| Some more aspects of optical cavities, and dielectric coatings for mirrors and such

|-
| 1.2.2021||[https://youtu.be/h2LeznCpPTk Optical fiber technology] || Some properties of optical fibers as the most common optical waveguide are covered, including optical mode spectrum, dispersion and transmission properties.

|-
| 8.2.2021||[https://youtu.be/xblN-KzMz0Y Optical modulators, part 1]
| rowspan = "2" | Many optical modulation techniques require rely on devices or materials where optical properties can be changed electrically; we cover accousto-optical and electro-optical devices, as well as liquid crystal systems.
|-
| 9.2.2021||[https://youtu.be/WfP5mahZrWU Optical modulators, part 2]

|-
| 15.2.2021
|[https://youtu.be/m_F4DOHMNeU Homodyne detection techniques] || Measurement of optical fields in many continuous variable scenarios require knowledge of optical homodyning and heterodyning techniques. These techniques, similar to their radiofrequency counterparts, rely on multiplying field amplitudes.

|-
| 1.3.2021
|[https://youtu.be/YkVlxxucLuA Frequency control of laser systems, part 1]
| rowspan="2" |Many laser systems in quantum technologies require to have a well-defined frequency relationship with atomic transitions or solid state qubits. We cover typical techniques how laser systems can be controlled to a high enough accuracy, utilizing spectroscopy techniques and control systems.
|-
| 2.3.2021
|[https://youtu.be/72aVZwI4BHU Frequency control of laser systems, part 2]

|-
| 8.3.2021
|[https://youtu.be/jolUa_EGZEs Interface to computers]
| High level interfacing between computers and electronic hardware: Standard device languages; some serial protocols, some aspects of microcontrollers and FPGAs

|-
| 15.3.2021
|[https://youtu.be/1S0EAnooQMc Pulses in quantum control]
| Many quantum systems require short control pulses, either in form of optical pulses or radiofrequency pulses. This covers how they are used, and present a few techniques to generate such control pulses

|-
| 22.3.2021
|[https://youtu.be/PHx-da7RLE8 High voltage techniques]
| Working with high voltages requires a spectrum of techniques that is differing from more conventional electronics. A few aspects (field emission, dielectric strength, specific components) are covered.

|-
|12.4.2021
|[https://youtu.be/K0U9ySRyvjs Control loops]
| Many experimental activities in controlling quantum systems require the control of classical systems, like the temperature stabilization of some device, or the frequency stabilization of a laser. This lecture gives a brief overview of some simple control concepts.

|-
| ||Practical aspects of superconducting systems || We cover different materials, transition temperatures, temperature measurement techniques and thermal insulation / conduction techniques.

|}

== Getting started ==
Consult the [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide] for information on using the wiki software.
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* Math can be entered in LaTeX style: <code><nowiki><math>r^2=\sqrt{x^2+y^2}</math></nowiki></code> renders as <math>r^2=\sqrt{x^2+y^2}</math>
* Should you miss any module or functionality of this wiki, please contact me (Christian Kurtsiefer).

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-28T18:53:24Z

Chua Rui Ming: /* Results */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
Product

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

Architecture

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

Preview

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. This produces two rather than one narrow pulse for every pair of clock signals- At the front-end and tail-end of the first and second clock signals respectively:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


[[File:2-Figure3-2.png||350px]]

For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

FPGA Top Design

[[File:Insert Image Here||300px]]

The FPGA Top Design summarises the outcome of our code behind the design of our FPGA. To characterise the performance of our FPGA, we measured the pulses produced by our FPGA (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals or the frequency of the clock signals we can obtain different performances (in terms of different pulse width and frequencies) of our FPGA. Hence, we characterised the performance of our FPGA as a function of the Phase Difference and as a function of Clock Frequency.

Pulses as a function of Phase Difference

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

Pulses as a function of Frequency

The clock frequency may be adjusted in integer multiples of the clock oscillator (refer to FPGA Architecture).

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

Summary Table

====Application====

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-28T18:23:59Z

Chua Rui Ming: /* Methods */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
Product

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

Architecture

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

Preview

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. This produces two rather than one narrow pulse for every pair of clock signals- At the front-end and tail-end of the first and second clock signals respectively:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


[[File:2-Figure3-2.png||350px]]

For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

FPGA Top Design

[[File:Insert Image Here||300px]]

The FPGA Top Design summarises the outcome of our code behind the design of our FPGA. To characterise the performance of our FPGA, we measured the pulses produced by our FPGA (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals or the frequency of the clock signals we can obtain different performances (in terms of different pulse width and frequencies) of our FPGA. Hence, we characterised the performance of our FPGA as a function of the Phase Difference and as a function of Clock Frequency.

Pulses as a function of Phase Difference

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

Pulses as a function of Frequency

The clock frequency may be adjusted in integer multiples of the clock oscillator (refer to FPGA Architecture).

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

Summary Table

====Application====

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

File:2-Figure3-2.png

2021-04-28T18:23:19Z

Chua Rui Ming: Chua Rui Ming uploaded a new version of File:2-Figure3-2.png

File:2-Figure3-2.png

2021-04-28T18:20:56Z

Chua Rui Ming: Chua Rui Ming uploaded a new version of File:2-Figure3-2.png

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-28T18:15:07Z

Chua Rui Ming: /* Methods */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
Product

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

Architecture

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

Preview

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. This produces two rather than one narrow pulse for every pair of clock signals- At the front-end and tail-end of the first and second clock signals respectively:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


[[File:2-Figure3-2.png||300px]]

For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

FPGA Top Design

[[File:Insert Image Here||300px]]

The FPGA Top Design summarises the outcome of our code behind the design of our FPGA. To characterise the performance of our FPGA, we measured the pulses produced by our FPGA (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals or the frequency of the clock signals we can obtain different performances (in terms of different pulse width and frequencies) of our FPGA. Hence, we characterised the performance of our FPGA as a function of the Phase Difference and as a function of Clock Frequency.

Pulses as a function of Phase Difference

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

Pulses as a function of Frequency

The clock frequency may be adjusted in integer multiples of the clock oscillator (refer to FPGA Architecture).

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

Summary Table

====Application====

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

File:2-Figure3-2.png

2021-04-28T18:14:08Z

Chua Rui Ming:

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-28T18:05:44Z

Chua Rui Ming: /* Results */

====Members====
Zhang Xing Jian A0226453H, Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter1 (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs1 (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications2 (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators3 (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
Product

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)4 (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant5 (Intel, n.d.). It measures 49 x 75.2mm.

Architecture

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li>
<li>594 Embedded memory (Kbits)</li>
<li>66 Embedded 18 x 18 multipliers</li>
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li>
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator4 (Terasic Technologies, n.d.).

Preview

The top and bottom view of the FPGA is featured below respectively4 (Terasic Technologies, n.d.).

[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows7 (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li>
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li>
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li>
</ul>
Architecture of Altera's FPGA's PLL7 (Intel, 2018)
 
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an A OR B operation to produce clock signal C
<li> The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse
[[File:2-Figure3-1.png||300px]]
</ul>

In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. This produces two rather than one narrow pulse for every pair of clock signals- At the front-end and tail-end of the first and second clock signals respectively:
<ul>

<li> The production of two clock signals A and B of the same frequency, with a phase shift.
<li> The implementation of an C = B XOR A operation to produce the narrow pulses
</ul>


For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub8,9 (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

FPGA Top Design

[[File:Insert Image Here||300px]]

The FPGA Top Design summarises the outcome of our code behind the design of our FPGA. To characterise the performance of our FPGA, we measured the pulses produced by our FPGA (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals or the frequency of the clock signals we can obtain different performances (in terms of different pulse width and frequencies) of our FPGA. Hence, we characterised the performance of our FPGA as a function of the Phase Difference and as a function of Clock Frequency.

Pulses as a function of Phase Difference

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

Pulses as a function of Frequency

The clock frequency may be adjusted in integer multiples of the clock oscillator (refer to FPGA Architecture).

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

[[File:Insert Image Here||300px]]

Summary Table

====Application====

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate

A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

2021-04-28T17:42:21Z

Chua Rui Ming: /* Methods */

File:2-Figure3-1.png

2021-04-28T17:36:21Z

Chua Rui Ming: Zhu & Wang's Method of Carving Pulses

== Summary ==
Zhu & Wang's Method of Carving Pulses