View source for A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)

====Members====
Zhang Xing Jian A0226453H,  Zhang Jian Ran A0226340R, Chua Rui Ming A0155387U

====Motivation====
Field Programmable Gate Arrays (FPGAs) offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility without the simplicity of the former and the functional complexity without the inflexibility of the latter<sup>1</sup> (Maxfield, 2008). Furthermore, they are cheap and easy to implement which enables small groups to meet their hardware and software needs<sup>1</sup> (Maxfield, 2008). As a result, FPGAs represent a useful option to the production of narrow pulses which finds its role in a myriad of scientific applications<sup>2</sup> (Zhu & Wang, 2015). In our context, the generation of narrow pulses is of particular interest in the field of integrated photonics, for example, in the carving of pump light into short pulses for Spontaneous Four-Wave Mixing (SFWM) in silicon microring resonators<sup>3</sup> (Ma, 2020). The use of FPGAs to produce narrow pulses provides us with a compact and adjustable pulse generator compatible with integrated photonics technology.

====FPGA Specifications====
<b>Product</b>

Our FPGA is the "DE0-Nano Development and Education Board" from Terasic (vendor)<sup>4</sup> (Terasic Technologies, n.d.). The FPGA utilises Intel Altera's Cyclone IV family, specifically, the Cyclone IV E variant<sup>5</sup> (Intel, n.d.). It measures 49 x 75.2mm. 

<b>Architecture</b> 

Some features of the make-up of our FPGA includes:
<ul>
<li>22,320 Logic Elements</li> 
<li>594 Embedded memory (Kbits)</li> 
<li>66 Embedded 18 x 18 multipliers</li> 
<li>4 General-purpose PLLs</li>
<li>53 Maximum FPGA I/O pins</li> 
</ul>

Its memory features 32MB Synchronous Dynamic Random-Access Memory (SDRAM), 2Kb I2C Electrically Erasable Programmable Read-Only Memories (EEPROM), and it has an on-board 50MHz clock oscillator<sup>4</sup> (Terasic Technologies, n.d.). 

<b>Preview</b>

The top and bottom view of the FPGA is featured below respectively<sup>4</sup> (Terasic Technologies, n.d.). 


[[File:DE0-Nano_layout_top.jpg||400px]]

[[File:DE0-Nano_layout_bot.jpg||400px]]

====Phase-Locked Loop (PLL) Module====

The PLL is the key component to our nanosecond pulse generator and would thus be elaborated upon in the following section. A PLL is a feedback control system that locks on the output signal of an oscillator to an input signal by monitoring and maintaining a phase between them. In Altera's FPGAs, the structure of the PLL is as follows<sup>7</sup> (Intel, 2018):
<ul>
<li> A "Phase Frequency Detector" is used to compare the feedback signal with the input signal for any errors between them</li> 
<li> A "Charge Pump" is used to convert said error, which manifests itself as an error signal, to a correction current</li> 
<li> A "Loop Filter" is used to produce a correction signal from the correction current which is subsequently used to regulate the oscillation frequency of the "Voltage Control Oscillator"</li>    
<li> The signal is then fed through the "Feedback Counter" back to the "Phase Frequency Detector" to complete the loop</li> 
</ul>
Architecture of Altera's FPGA's PLL<sup>7</sup> (Intel, 2018)  
<br>
[[File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png||600px]]

====Methods====

Since the PLL is reconfigurable, the phase, frequency and bandwidth of the PLL output signal may be adjusted in real-time. Logic operations may be executed on two signals produced by the PLL to "carve" out the difference between the two signals into a desired narrow pulse. In Zhu & Wang's paper (2015), they utilised the steps and logic operations to obtain such a pulse:
<ul>
<i>
<li> <span style="color:blue;">The production of two clock signals A and B of the same frequency, with a phase shift.</span>
<li> <span style="color:blue;">The implementation of an A OR B operation to produce clock signal C</span>
<li> <span style="color:blue;">The implementation of a D = C XOR A operation to carve out the difference between the two signals to produce the narrow pulse</span> 
[[File:2-Figure3-1.png||300px]]
</ul>
</i>
In our case, our method deviates from that of Zhu & Wang by implementing a two-step procedure to carve out the pulse. This was achieved simply by skipping the A OR B operation. There are two reasons for our choice: Firstly, this simplifies the problem. Secondly, this way, we obtain two pulses for every set of clock signals- At the front-end and tail-end of the first and second clock signals respectively:

<ul>
<i>
<li> <span style="color:blue;">The production of two clock signals A and B of the same frequency, with a phase shift.</span>
<li> <span style="color:red;">The implementation of an C = B XOR A operation to produce the narrow pulses</span>
</ul>
</i>
</p>
[[File:2-Figure3-2.png||350px]]
</p>
For the uninitiated, the OR and XOR logic operation can be described by the truth tables and illustrated by the pulsed operations below as referenced from Electronics Hub<sup>8,</sup><sup>9</sup> (Electronics Hub, 2017)

[[File:OR.jpg||300px]] [[File:OR Pulsed.jpg||300px]]

[[File:XOR.jpg||200px]] [[File:XOR Pulsed.jpg||250px]]

====Results====

<b>FPGA Top Design</b>

[[File:Top_Design.png|1200px]]

The bulk of our efforts went into the code to configure the Nanosecond Pulse Generator. The FPGA Top Design summarises the outcome of our efforts. Our efforts in its entirety could be found here https://drive.google.com/drive/folders/1weGO1Lyi6H_-A1OadQFYIO-wQEv0VXFj?usp=sharing which will lead to a Google Drive where our files are uploaded in its entirety. 

<b>FPGA Performance Characterisation</b>

To characterise the performance of our FPGA, we measured the pulses produced by our FPGA with an oscilloscope (see below). We recall that one of the strengths of the FPGA lies in its adjustability; By adjusting the phase difference between the clock signals, and/or the frequency of the clock signals (which can be adjusted in integer multiples of the clock oscillator), we can obtain different performances (in terms of pulse widths and frequencies) of our pulses.
<br>
<br>
<b>1) Best Overall Performance</b> 

The best overall performance was obtained when the phase difference between the clock signals was set at 11.25 degrees while the frequency of the clock signal is 150MHZ. We obtained a <span style="color:blue;">pulse width of 637ps</span> at a <span style="color:blue;">frequency of 150MHZ</span>. 

[[File:d11.25f150_Best_Performance.png|600px]]

Unfortunately, pushing the FPGA further, we were unable to obtain narrower pulses with that higher frequencies.

[[File:D10f200 Too High Frequency For Pulse Width.png||600px]]

<b>2) Highest Frequency </b>

The best frequency performance was obtained when the phase difference between the clock signals was set at 15 degrees while the frequency of the clock signal is 200MHZ. We obtained a <span style="color:blue;">pulse width of 746 ps</span> at a <span style="color:blue;">frequency of 200MHZ</span>. 

[[File:D15f200 _Best _Frequency.png||600px]]

<b>3) Results as a Function of Phase Difference </b>

We recall from "Methods" that the way to obtain the pulses was to carve the pulses out from two clock signals. Theoretically, the pulse duration should increase with phase difference for the same frequency. When the phase difference between the clock signals were set at 9, 18 and 37.5 degrees and the frequency of the clock signal is 100MHZ, we obtained a <span style="color:blue;">pulse width of 805 ps</span>, <span style="color:blue;">pulse width of 1.2 ns</span> and <span style="color:blue;">pulse width of 2.27ns</span> respectively. 

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]]

[[File:D18f100_Function_Of_Phase_Difference_2.png||600px]]

[[File:D37.5f100_Function_Of_Phase_Difference_3.png||600px]]

<b>4) Different Configurations For The Same Pulse Width (Theoretically) </b>

Theoretically, the pulse duration should remain the same if the phase difference and frequency were increased with the same multiple. The plots below feature such a measurement. 

[[File:D3.37f50.png||600px]] 

[[File:D9f100_Function_Of_Phase_Difference_1.png||600px]] 

[[File:D11.25f150_Best_Performance.png||600px]] 

<b>Summary Table</b>

====Application====

While we have achieved our goal of creating a working Nanosecond Pulse Generator with our FPGA similar to the works of Zhu & Wang, it is important to recognise the fact that the pulses created by the FPGA belong to low-power pulse signals between 1.2-3.3V based on the specific I/O standard for the FPGA. 

Amplification may be required for our FPGA to work with other devices. In this section, we designed an amplifier with the intention of amplifying our pulses up to 7.8V based on the following schematics.  

[[File:Amplifier.png||400px]]

[[File:Amplifer_2.jpg||300px]]

====References====
[1] Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.

[2] Zhu, Y., &amp; Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78

[3] Ma, C. (2020). High-Quality Photon Pair Generation in Silicon Photonic Microring and Its Applications. UC San Diego. ProQuest ID: Ma_ucsd_0033D_19192. Merritt ID: ark:/13030/m5sf83ns. Retrieved from https://escholarship.org/uc/item/7ws930nj

[4] Terasic Technologies. (n.d.). All FPGA boards - Cyclone IV - DE0-Nano development and Education Board. Retrieved March 23, 2021, from https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&amp;CategoryNo=139&amp;No=593&amp;PartNo=3#section

[5] Intel. (n.d.). Cyclone® IV Fpgas devices - Intel® FPGA. Retrieved March 23, 2021, from https://www.intel.sg/content/www/xa/en/products/programmable/fpga/cyclone-iv.html

[6] Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html

[7] Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html

[8] Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate

[9] Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate