A temperature-tunable etalon for optical telecommunication wavelength: Difference between revisions
No edit summary |
|||
| Line 60: | Line 60: | ||
==Temperature Tuning of silicon etalon== | ==Temperature Tuning of silicon etalon== | ||
A small piece of the silicon wafer is mounted on a copper block with a 4mm diameter hole through hole. The copper serves as a thermally conductive mount for the silicon etalon and is placed on top of a Peltier stage. The temperature of this entire stack is adjusted and stabilized with a TEC controller. A few different temperatures were tried. | |||
[[File:100um-whole.png|options|Transmission spectrum of a bare silicon wafer of 100μm]] | |||
Revision as of 23:56, 8 March 2021
Members
Shi Yicheng (A0054800R), Du Jinyi (A0227185B), Zhang Qian(A0228752Y)
Rationale
A Fabry-Perot interferometer (or an Etalon), being probably the simplest form of all interferometers, is found useful in a variety of optical applications such as spectral filtering or frequency referencing.
An etalon is typically constructed out of the two parallel reflecting surfaces of a transparent plate. The plate needs to have low absorption loss for the desired working wavelengths to ensure a relatively high finesse of the etalon. The material choice for visible wavelengths is usually fused silica with an absorption coefficient of [bla] and a thermal expansion coefficient of [bla].
For optical telecommunication wavelengths, which range from about 1260nm to 1625nm, pure silicon becomes a more practical choice with an absorption coefficient of [bla] and thermal expansion coefficient of [bla].
Characteristic Parameters of an Etalon
The performance of etalon is characterized by several main parameters: including visibility (V), free spectral range (FSR), full width half maximum (FWHM), and central wavelength.
Suppose that the , , are the electrical field intensity of input, oscillating, output light.
The relationship is as follows
Where \phi means that phase delay in the cavity and the gap between two reflective surfaces is d.
From the upper two equations, we have
Then, we can calculate the transmission ratio:
Here, we have
So, can be simplified as follows
Here, we define a new parameter: , which is called coefficient finesse.
So,
Building an Etalon Out of Silicon Wafer
Design
(this section will stay empty for a long time...)
Performance
Bare Silicon Wafer
HR Coated Silicon Wafer
Temperature Tuning of silicon etalon
A small piece of the silicon wafer is mounted on a copper block with a 4mm diameter hole through hole. The copper serves as a thermally conductive mount for the silicon etalon and is placed on top of a Peltier stage. The temperature of this entire stack is adjusted and stabilized with a TEC controller. A few different temperatures were tried.

