A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs): Difference between revisions
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Field Programmable Gate Arrays offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility but simplicity of the former and the functional complexity but inflexibility of the latter (Maxfield, 2008). | Field Programmable Gate Arrays offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility but simplicity of the former and the functional complexity but inflexibility of the latter (Maxfield, 2008). They are cheap and easy to implement which enables small groups to meet their hardware and software needs (Maxfield, 2008). | ||
====Field Programmable Gate Arrays (FPGAs)==== | ====Field Programmable Gate Arrays (FPGAs)==== | ||
Revision as of 14:11, 23 March 2021
Members
Zhang Xing Jian, Jian Ran, Chua Rui Ming
Motivation
Field Programmable Gate Arrays offer both the advantage of Programmable Logic Devices (PLDs) and Application Specific Integrated Circuits (ASICs) because it possesses the functional flexibility but simplicity of the former and the functional complexity but inflexibility of the latter (Maxfield, 2008). They are cheap and easy to implement which enables small groups to meet their hardware and software needs (Maxfield, 2008).
Field Programmable Gate Arrays (FPGAs)
Phase-Locked Loop (PLL) Module
References
Intel. (2020). Intel® Quartus® Prime Software Suite. The Intuitive High-Performance Design Environment. Retrieved March 22, 2021, from https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html
Maxfield, C. (2008). Fpgas: Instant access. In FPGAs: Instant access (1st ed., pp. 1-12). Burlington, MA: Newnes/Elsevier.
Zhu, Y., & Wang, L. (2015). Design and implementation of nanosecond Pulse generator based ON RECONFIGURATION PLL in FPGA. Proceedings of the 2015 International Conference on Electronic Science and Automation Control. doi:10.2991/esac-15.2015.78