User contributions for Chua Rui Ming

Results for Chua Rui Ming talk block log uploads logs
A user with 98 edits. Account created on 15 February 2021.

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17:4317:43, 30 April 2021 diff hist 0 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Summary Table
17:4317:43, 30 April 2021 diff hist 0 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Summary Table
17:4317:43, 30 April 2021 diff hist +2 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Application
17:4217:42, 30 April 2021 diff hist −3 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Application
17:4217:42, 30 April 2021 diff hist +5 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Application
17:4117:41, 30 April 2021 diff hist +78 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Application
17:3817:38, 30 April 2021 diff hist +68 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Application
17:3517:35, 30 April 2021 diff hist −8 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Application
17:3417:34, 30 April 2021 diff hist 0 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Application
17:3317:33, 30 April 2021 diff hist +18 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Application
17:3317:33, 30 April 2021 diff hist +285 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Application
17:2417:24, 30 April 2021 diff hist +36 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Different Configurations For The Same Pulse Width (Theoretically)
17:2017:20, 30 April 2021 diff hist +231 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Different Configurations For The Same Pulse Width (Theoretically)
17:1717:17, 30 April 2021 diff hist −13 Main Page →A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) current
17:1517:15, 30 April 2021 diff hist −12 Main Page →A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)
17:1517:15, 30 April 2021 diff hist +12 Main Page →A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)
17:0717:07, 30 April 2021 diff hist +27 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Summary Table
17:0617:06, 30 April 2021 diff hist 0 N File:Table.png No edit summary current
17:0517:05, 30 April 2021 diff hist +3 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Results
17:0317:03, 30 April 2021 diff hist −1 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Product
17:0217:02, 30 April 2021 diff hist +10 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →FPGA Specifications

18:3818:38, 29 April 2021 diff hist +576 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Application
18:2218:22, 29 April 2021 diff hist 0 N File:Amplifer 2.jpg No edit summary current
18:2118:21, 29 April 2021 diff hist 0 N File:Amplifier.png No edit summary current
18:1918:19, 29 April 2021 diff hist +1,668 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Results
18:0018:00, 29 April 2021 diff hist 0 N File:D3.37f50.png No edit summary current
17:5117:51, 29 April 2021 diff hist 0 N File:D37.5f100 Function Of Phase Difference 3.png No edit summary current
17:5117:51, 29 April 2021 diff hist 0 N File:D18f100 Function Of Phase Difference 2.png No edit summary current
17:5017:50, 29 April 2021 diff hist +35 N File:D9f100 Function Of Phase Difference 1.png Function of Frequency current
17:3617:36, 29 April 2021 diff hist +28 N File:D15f200 Best Frequency.png Best Frequency current
17:2117:21, 29 April 2021 diff hist +111 N File:D10f200 Too High Frequency For Pulse Width.png Tried to maintain the narrow pulse width while pushing the pulse frequency up. Limit was reached. current
17:1317:13, 29 April 2021 diff hist +43 N File:D11.25f150 Best Performance.png Best Performance of our FPGA! current
16:4016:40, 29 April 2021 diff hist −9 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Results
14:1714:17, 29 April 2021 diff hist +19 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Results
13:5513:55, 29 April 2021 diff hist +303 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Results
13:2613:26, 29 April 2021 diff hist 0 File:Top Design.png Chua Rui Ming uploaded a new version of File:Top Design.png current
13:1113:11, 29 April 2021 diff hist −4 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Results
13:0813:08, 29 April 2021 diff hist −81 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Methods
13:0813:08, 29 April 2021 diff hist +149 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Methods
13:0513:05, 29 April 2021 diff hist +29 N File:Top Design.png FPGA Top Design
03:0103:01, 29 April 2021 diff hist +12 Main Page →A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs)
02:5302:53, 29 April 2021 diff hist +7 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Results
02:2302:23, 29 April 2021 diff hist 0 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Methods
02:2302:23, 29 April 2021 diff hist 0 File:2-Figure3-2.png Chua Rui Ming uploaded a new version of File:2-Figure3-2.png current
02:2002:20, 29 April 2021 diff hist 0 File:2-Figure3-2.png Chua Rui Ming uploaded a new version of File:2-Figure3-2.png
02:1502:15, 29 April 2021 diff hist +37 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Methods
02:1402:14, 29 April 2021 diff hist 0 N File:2-Figure3-2.png No edit summary
02:0502:05, 29 April 2021 diff hist +978 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Results
01:4201:42, 29 April 2021 diff hist +797 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Methods
01:3601:36, 29 April 2021 diff hist +51 N File:2-Figure3-1.png Zhu & Wang's Method of Carving Pulses current

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