Main public logs

Combined display of all available logs of QT5201U wiki. You can narrow down the view by selecting a log type, the username (case-sensitive), or the affected page (also case-sensitive).

• 17:06, 30 April 2021 Chua Rui Ming talk contribs created page File:Table.png
• 17:06, 30 April 2021 Chua Rui Ming talk contribs uploaded File:Table.png
• 18:22, 29 April 2021 Chua Rui Ming talk contribs created page File:Amplifer 2.jpg
• 18:22, 29 April 2021 Chua Rui Ming talk contribs uploaded File:Amplifer 2.jpg
• 18:21, 29 April 2021 Chua Rui Ming talk contribs created page File:Amplifier.png
• 18:21, 29 April 2021 Chua Rui Ming talk contribs uploaded File:Amplifier.png
• 18:00, 29 April 2021 Chua Rui Ming talk contribs created page File:D3.37f50.png
• 18:00, 29 April 2021 Chua Rui Ming talk contribs uploaded File:D3.37f50.png
• 17:51, 29 April 2021 Chua Rui Ming talk contribs created page File:D37.5f100 Function Of Phase Difference 3.png
• 17:51, 29 April 2021 Chua Rui Ming talk contribs uploaded File:D37.5f100 Function Of Phase Difference 3.png
• 17:51, 29 April 2021 Chua Rui Ming talk contribs created page File:D18f100 Function Of Phase Difference 2.png
• 17:51, 29 April 2021 Chua Rui Ming talk contribs uploaded File:D18f100 Function Of Phase Difference 2.png
• 17:50, 29 April 2021 Chua Rui Ming talk contribs created page File:D9f100 Function Of Phase Difference 1.png (Function of Frequency)
• 17:50, 29 April 2021 Chua Rui Ming talk contribs uploaded File:D9f100 Function Of Phase Difference 1.png (Function of Frequency)
• 17:36, 29 April 2021 Chua Rui Ming talk contribs created page File:D15f200 Best Frequency.png (Best Frequency)
• 17:36, 29 April 2021 Chua Rui Ming talk contribs uploaded File:D15f200 Best Frequency.png (Best Frequency)
• 17:21, 29 April 2021 Chua Rui Ming talk contribs created page File:D10f200 Too High Frequency For Pulse Width.png (Tried to maintain the narrow pulse width while pushing the pulse frequency up. Limit was reached.)
• 17:21, 29 April 2021 Chua Rui Ming talk contribs uploaded File:D10f200 Too High Frequency For Pulse Width.png (Tried to maintain the narrow pulse width while pushing the pulse frequency up. Limit was reached.)
• 17:13, 29 April 2021 Chua Rui Ming talk contribs created page File:D11.25f150 Best Performance.png (Best Performance of our FPGA!)
• 17:13, 29 April 2021 Chua Rui Ming talk contribs uploaded File:D11.25f150 Best Performance.png (Best Performance of our FPGA!)
• 13:26, 29 April 2021 Chua Rui Ming talk contribs uploaded a new version of File:Top Design.png
• 13:05, 29 April 2021 Chua Rui Ming talk contribs created page File:Top Design.png (FPGA Top Design)
• 13:05, 29 April 2021 Chua Rui Ming talk contribs uploaded File:Top Design.png (FPGA Top Design)
• 02:23, 29 April 2021 Chua Rui Ming talk contribs uploaded a new version of File:2-Figure3-2.png
• 02:20, 29 April 2021 Chua Rui Ming talk contribs uploaded a new version of File:2-Figure3-2.png
• 02:14, 29 April 2021 Chua Rui Ming talk contribs created page File:2-Figure3-2.png
• 02:14, 29 April 2021 Chua Rui Ming talk contribs uploaded File:2-Figure3-2.png
• 01:36, 29 April 2021 Chua Rui Ming talk contribs created page File:2-Figure3-1.png (Zhu & Wang's Method of Carving Pulses)
• 01:36, 29 April 2021 Chua Rui Ming talk contribs uploaded File:2-Figure3-1.png (Zhu & Wang's Method of Carving Pulses)
• 16:53, 29 March 2021 Chua Rui Ming talk contribs created page File:OR Pulsed.jpg (Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate)
• 16:53, 29 March 2021 Chua Rui Ming talk contribs uploaded File:OR Pulsed.jpg (Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate)
• 16:52, 29 March 2021 Chua Rui Ming talk contribs created page File:XOR Pulsed.jpg (Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate)
• 16:52, 29 March 2021 Chua Rui Ming talk contribs uploaded File:XOR Pulsed.jpg (Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate)
• 16:52, 29 March 2021 Chua Rui Ming talk contribs created page File:XOR.jpg (Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate)
• 16:52, 29 March 2021 Chua Rui Ming talk contribs uploaded File:XOR.jpg (Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate)
• 16:51, 29 March 2021 Chua Rui Ming talk contribs created page File:OR.jpg (Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate)
• 16:51, 29 March 2021 Chua Rui Ming talk contribs uploaded File:OR.jpg (Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate)
• 03:10, 24 March 2021 Chua Rui Ming talk contribs created page File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png (Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html)
• 03:10, 24 March 2021 Chua Rui Ming talk contribs uploaded File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png (Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html)
• 01:38, 24 March 2021 Chua Rui Ming talk contribs created page File:DE0-Nano layout bot.jpg
• 01:38, 24 March 2021 Chua Rui Ming talk contribs uploaded File:DE0-Nano layout bot.jpg
• 01:38, 24 March 2021 Chua Rui Ming talk contribs created page File:DE0-Nano layout top.jpg
• 01:38, 24 March 2021 Chua Rui Ming talk contribs uploaded File:DE0-Nano layout top.jpg
• 02:31, 23 March 2021 Chua Rui Ming talk contribs created page A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) (Created page with "====Members==== Zhang Xing Jian, Jian Ran, Chua Rui Ming ====Motivation==== Field Programmable Gate Arrays offer both the advantage of Programmable Logic Devices (PLDs) and A...")