Uploads by Chua Rui Ming
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This special page shows all uploaded files.
| Date | Name | Thumbnail | Size | Description | Versions |
|---|---|---|---|---|---|
| 17:06, 30 April 2021 | Table.png (file) |  |
25 KB | 1 | |
| 18:22, 29 April 2021 | Amplifer 2.jpg (file) |  |
120 KB | 1 | |
| 18:21, 29 April 2021 | Amplifier.png (file) |  |
13 KB | 1 | |
| 18:00, 29 April 2021 | D3.37f50.png (file) |  |
48 KB | 1 | |
| 17:51, 29 April 2021 | D37.5f100 Function Of Phase Difference 3.png (file) |  |
53 KB | 1 | |
| 17:51, 29 April 2021 | D18f100 Function Of Phase Difference 2.png (file) |  |
58 KB | 1 | |
| 17:50, 29 April 2021 | D9f100 Function Of Phase Difference 1.png (file) |  |
46 KB | Function of Frequency | 1 |
| 17:36, 29 April 2021 | D15f200 Best Frequency.png (file) |  |
55 KB | Best Frequency | 1 |
| 17:21, 29 April 2021 | D10f200 Too High Frequency For Pulse Width.png (file) |  |
70 KB | Tried to maintain the narrow pulse width while pushing the pulse frequency up. Limit was reached. | 1 |
| 17:13, 29 April 2021 | D11.25f150 Best Performance.png (file) |  |
49 KB | Best Performance of our FPGA! | 1 |
| 13:26, 29 April 2021 | Top Design.png (file) |  |
17 KB | 2 | |
| 02:23, 29 April 2021 | 2-Figure3-2.png (file) |  |
11 KB | 3 | |
| 01:36, 29 April 2021 | 2-Figure3-1.png (file) |  |
12 KB | Zhu & Wang's Method of Carving Pulses | 1 |
| 16:53, 29 March 2021 | OR Pulsed.jpg (file) |  |
13 KB | Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate | 1 |
| 16:52, 29 March 2021 | XOR Pulsed.jpg (file) |  |
16 KB | Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate | 1 |
| 16:52, 29 March 2021 | XOR.jpg (file) |  |
9 KB | Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate | 1 |
| 16:51, 29 March 2021 | OR.jpg (file) |  |
15 KB | Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate | 1 |
| 03:10, 24 March 2021 | Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png (file) | _IP_Core_User_Guide.png) |
41 KB | Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html | 1 |
| 01:38, 24 March 2021 | DE0-Nano layout bot.jpg (file) |  |
1.27 MB | 1 | |
| 01:38, 24 March 2021 | DE0-Nano layout top.jpg (file) |  |
953 KB | 1 |
