User contributions for Chua Rui Ming

28 April 2021

• 18:2918:29, 28 April 2021 diff hist +109 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Results

25 April 2021

• 18:1918:19, 25 April 2021 diff hist +38 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Methods

29 March 2021

• 16:5916:59, 29 March 2021 diff hist 0 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Methods
• 16:5616:56, 29 March 2021 diff hist +110 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Methods
• 16:5316:53, 29 March 2021 diff hist +167 N File:OR Pulsed.jpg Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate current
• 16:5216:52, 29 March 2021 diff hist +178 N File:XOR Pulsed.jpg Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate current
• 16:5216:52, 29 March 2021 diff hist +178 N File:XOR.jpg Electronics Hub. (2017, December 24). Exclusive or Gate(XOR-Gate). Retrieved March 29, 2021, from https://www.electronicshub.org/exclusive-or-gatexor-gate/#XOR_Gate current
• 16:5116:51, 29 March 2021 diff hist +167 N File:OR.jpg Electronics Hub. (2017, December 24). Digital logic or gate. Retrieved March 29, 2021, from https://www.electronicshub.org/digital-logic-or-gate/#OR_Gate current
• 16:5016:50, 29 March 2021 diff hist 0 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Methods
• 16:5016:50, 29 March 2021 diff hist +329 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →References
• 16:4816:48, 29 March 2021 diff hist +866 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Phase-Locked Loop (PLL) Module

24 March 2021

• 17:3817:38, 24 March 2021 diff hist +26 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Phase-Locked Loop (PLL) Module
• 17:3617:36, 24 March 2021 diff hist +9 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Phase-Locked Loop (PLL) Module
• 17:3417:34, 24 March 2021 diff hist +706 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Phase-Locked Loop (PLL) Module
• 16:5516:55, 24 March 2021 diff hist +154 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Phase-Locked Loop (PLL) Module
• 16:3916:39, 24 March 2021 diff hist +125 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Phase-Locked Loop (PLL) Module
• 16:1616:16, 24 March 2021 diff hist +150 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →FPGA Specifications
• 03:1203:12, 24 March 2021 diff hist +78 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Phase-Locked Loop (PLL) Module
• 03:1003:10, 24 March 2021 diff hist +219 N File:Altera Phase-Locked Loop (Altera PLL) IP Core User Guide.png Intel. (2018, December 20). Altera phase-locked Loop (ALTERA PLL) ip core user guide. Retrieved March 23, 2021, from https://www.intel.com/content/www/us/en/programmable/documentation/mcn1401782837027.html current
• 03:0903:09, 24 March 2021 diff hist +59 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →FPGA Specifications
• 03:0603:06, 24 March 2021 diff hist +70 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →FPGA Specifications
• 03:0503:05, 24 March 2021 diff hist +105 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →FPGA Specifications
• 02:5702:57, 24 March 2021 diff hist +12 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →FPGA Specifications
• 02:4502:45, 24 March 2021 diff hist +102 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →FPGA Specifications
• 02:3702:37, 24 March 2021 diff hist +16 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →References
• 02:3502:35, 24 March 2021 diff hist +12 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →References
• 02:3402:34, 24 March 2021 diff hist +24 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →FPGA Specifications
• 02:3302:33, 24 March 2021 diff hist 0 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Motivation
• 02:3302:33, 24 March 2021 diff hist +48 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Motivation
• 02:2302:23, 24 March 2021 diff hist +426 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →References
• 02:2202:22, 24 March 2021 diff hist +392 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →FPGA Specifications
• 01:5401:54, 24 March 2021 diff hist 0 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →FPGA Specifications
• 01:5401:54, 24 March 2021 diff hist −40 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →FPGA Specifications
• 01:5301:53, 24 March 2021 diff hist +52 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →FPGA Specifications
• 01:5201:52, 24 March 2021 diff hist +10 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →FPGA Specifications
• 01:5101:51, 24 March 2021 diff hist +58 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →FPGA Specifications
• 01:3801:38, 24 March 2021 diff hist 0 N File:DE0-Nano layout bot.jpg No edit summary current
• 01:3801:38, 24 March 2021 diff hist 0 N File:DE0-Nano layout top.jpg No edit summary current
• 01:3701:37, 24 March 2021 diff hist −19 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Field Programmable Gate Arrays (FPGAs)
• 00:4100:41, 24 March 2021 diff hist +207 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →References

23 March 2021

• 23:0823:08, 23 March 2021 diff hist +1 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Motivation
• 23:0723:07, 23 March 2021 diff hist +13 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Motivation
• 23:0123:01, 23 March 2021 diff hist +16 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Motivation
• 17:5517:55, 23 March 2021 diff hist +242 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →References
• 17:5217:52, 23 March 2021 diff hist +30 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Members
• 17:5117:51, 23 March 2021 diff hist +290 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Motivation
• 14:4414:44, 23 March 2021 diff hist +7 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Members
• 14:3914:39, 23 March 2021 diff hist +282 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Motivation
• 14:1114:11, 23 March 2021 diff hist +123 A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) →Motivation
• 02:3102:31, 23 March 2021 diff hist +1,089 N A Nanosecond Pulse Generator based on the Reconfigurable Phase-Locked Loop (PLL) Module in Field Programmable Gate Arrays (FPGAs) Created page with "====Members==== Zhang Xing Jian, Jian Ran, Chua Rui Ming ====Motivation==== Field Programmable Gate Arrays offer both the advantage of Programmable Logic Devices (PLDs) and A..."